PIC18F4580-I/ML Microchip Technology, PIC18F4580-I/ML Datasheet - Page 144

• Manufacturer Part Number: PIC18F4580-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
TABLE 11-7:
DS39637D-page 144
RD0/PSP0/
C1IN+
RD1/PSP1/
C1IN-
RD2/PSP2/
C2IN+
RD3/PSP3/
C2IN-
RD4/PSP4/
ECCP1/P1A
RD5/PSP5/
P1B
RD6/PSP6/
P1C
RD7/PSP7/
P1D
Legend:
Pin Name
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input
RD6
PSP6
P1C
RD7
PSP7
P1D
Function
ECCP1
C1IN+
C2IN+
PSP0
PSP1
C1IN-
PSP2
PSP3
C2IN-
PSP4
PSP5
RD0
RD1
RD2
RD3
RD4
RD5
P1A
P1B
PORTD I/O SUMMARY
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
TRIS
0
1
x
x
1
0
1
x
x
1
0
1
x
x
1
0
1
x
x
1
0
1
x
x
0
1
0
0
1
X
x
0
0
1
x
x
0
0
1
x
x
0
Buffer
ANA
ANA
ANA
ANA
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATD<0> data output.
PORTD<0> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled).
Comparator 1 Positive Input B. Default on POR. This analog input overrides the
digital input (read as clear – low level).
LATD<1> data output.
PORTD<1> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<1> control when
enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<1> control when enabled).
Comparator 1 negative input. Default on POR. This analog input overrides the
digital input (read as clear – low level).
LATD<2> data output.
PORTD<2> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<2> control when
enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<2> control when enabled).
Comparator 2 positive input. Default on POR. This analog input overrides the digital
input (read as clear – low level).
LATD<3> data output.
PORTD<3> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<3> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<3> control when enabled).
Comparator 2 negative input. Default input on POR. This analog input overrides the
digital input (read as clear – low level).
LATD<4> data output.
PORTD<4> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<4> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<4> control when enabled).
ECCP1 compare output.
ECCP1 capture input.
ECCP1 Enhanced PWM output, Channel A.
LATD<5> data output.
PORTD<5> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<5> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<5> control when enabled).
ECCP1 Enhanced PWM output, Channel B.
LATD<6> data output.
PORTD<6> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<6> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<6> control when enabled).
ECCP1 Enhanced PWM output, Channel C.
LATD<7> data output.
PORTD<7> data input.
Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled).
Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled).
ECCP1 Enhanced PWM output, channel D.
Description
© 2009 Microchip Technology Inc.