LM93CIMT National Semiconductor, LM93CIMT Datasheet - Page 64

• Manufacturer Part Number: LM93CIMT
• Description: Microprocessor Support IC
• Manufacturer: National Semiconductor

Specifications of LM93CIMT

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Supply Voltage Min: 3V
• Operating Temperature Min: 0��C
• Package / Case: 56-TSSOP
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Register
Address
Register
Address
16.0 Registers
16.8.4 Register BFh PWM Ramp Control
If the time delay between steps is set to 0 ms, the PWM duty cycle goes immediately to 100% instead of ramping up gradually.
16.8.5 Register C0h Fan Boost Hysteresis (Zones 1/2)
If the temperature zone is above fan boost temperature and then drops below the fan boost temperature, the following occurs:
the PWM output remains at 100% until the temperature goes a certain amount below the fan boost temperature. These hysteresis
registers control this amount and can be set anywhere from 0˚C to 15˚C (unsigned).
BFh
C0h
Read/
Read/
Write
Write
R/W
R/W
3:0
7:4
3:0
7:4
Bit
Bit
PWM Ramp
(Zones 1/2)
Fan Boost
Hysteresis
Register
Register
(Continued)
Control
Name
Name
VRD_RAMP
PH_RAMP
Name
Name
H1
H2
or PH_RAMP
VRD_RAMP
Bit 7
Bit 7
Ah
Bh
Ch
Dh
Eh
Fh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
R/W
R/W
R/W
R/W
R/W
R/W
Bit 6
Bit 6
PH_RAMP
Sets the time delay between ramp steps for the
VRDx_HOT ramp up/ramp down PWM function.
Sets the time delay between ramp steps for the
Px_PROCHOT ramp up/ramp down PWM function.
Sets the fan boost hysteresis for zone 1
Sets the fan boost hysteresis for zone 2
H2
Bit 5
Bit 5
64
Time Delay between
Bit 4
Bit 4
Ramp Steps
100 ms
150 ms
200 ms
250 ms
300 ms
350 ms
400 ms
450 ms
500 ms
550 ms
600 ms
650 ms
700 ms
750 ms
50 ms
0 ms
Description
Description
Bit 3
Bit 3
Bit 2
Bit 2
VRD_RAMP
H1
Bit 1
Bit 1
Bit 0
Bit 0
Default
Default
Value
Value
44h
00h