DSPIC30F6010AT-30I/PF Microchip Technology, DSPIC30F6010AT-30I/PF Datasheet - Page 82
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DSPIC30F6010AT-30I/PF
Manufacturer Part Number
DSPIC30F6010AT-30I/PF
Description
IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6011A-30IPT.pdf
(6 pages)
4.DSPIC30F6015-30IPT.pdf
(232 pages)
5.DSPIC30F6015-30IPT.pdf
(14 pages)
6.DSPIC30F6015-30IPT.pdf
(12 pages)
7.DSPIC30F6015-30IPT.pdf
(18 pages)
8.DSPIC30F6010A-30IPF.pdf
(22 pages)
Specifications of DSPIC30F6010AT-30I/PF
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010AT-30I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F6010A/6015
12.1.2
Each capture channel has an associated FIFO buffer,
which is four 16-bit words deep. There are two status
flags, which provide status on the FIFO buffer:
• ICBNE – Input Capture Buffer Not Empty
• ICOV – Input Capture Overflow
The ICBFNE will be set on the first input capture event
and remain set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition will occur and the
ICOV bit will be set to a logic ‘1’. The fifth capture event
is lost and is not stored in the FIFO. No additional
events will be captured till all four events have been
read from the buffer.
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.
12.1.3
Each capture channel can select between one of two
timers for the time base, Timer2 or Timer3.
Selection of the timer resource is accomplished
through SFR bit ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
12.1.4
When the input capture module is set for capture on
every edge, rising and falling, ICM<2:0> = 001, the
following operations are performed by the input
capture logic:
• The input capture interrupt flag is set on every
• The interrupt on Capture mode setting bits,
• A capture overflow condition is not generated in
DS70150D-page 82
edge, rising and falling.
ICI<1:0>, is ignored, since every capture
generates an interrupt.
this mode.
CAPTURE BUFFER OPERATION
TIMER2 AND TIMER3 SELECTION
MODE
HALL SENSOR MODE
12.2
An input capture event will generate a device wake-up
or interrupt, if enabled, if the device is in CPU Idle or
Sleep mode.
Independent of the timer being enabled, the input
capture module will wake-up from the CPU Sleep or Idle
mode when a capture event occurs, if ICM<2:0> = 111
and the interrupt enable bit is asserted. The same wake-
up can generate an interrupt, if the conditions for pro-
cessing the interrupt have been satisfied. The wake-up
feature is useful as a method of adding extra external pin
interrupts.
12.2.1
CPU Sleep mode allows input capture module
operation with reduced functionality. In the CPU Sleep
mode, the ICI<1:0> bits are not applicable, and the
input capture module can only function as an external
interrupt source.
The capture module must be configured for interrupt
only on the rising edge (ICM<2:0> = 111), in order for
the input capture module to be used while the device
is in Sleep mode. The prescale settings of 4:1 or 16:1
are not applicable in this mode.
12.2.2
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the Interrupt
mode selected by the ICI<1:0> bits is applicable, as well
as the 4:1 and 16:1 capture prescale settings, which are
defined by control bits ICM<2:0>. This mode requires
the selected timer to be enabled. Moreover, the ICSIDL
bit must be asserted to a logic ‘0’.
If
ICM<2:0> = 111 in CPU Idle mode, the input capture
pin will serve only as an external interrupt pin.
12.3
The input capture channels have the ability to generate
an interrupt, based upon the selected number of
capture events. The selection number is set by control
bits ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective Capture Channel Interrupt Flag is located in
the corresponding IFSx STATUS register.
Enabling an interrupt is accomplished via the
respective Capture Channel Interrupt Enable (ICxIE)
bit. The Capture Interrupt Enable bit is located in the
corresponding IEC Control register.
the
Input Capture Operation During
Sleep and Idle Modes
Input Capture Interrupts
input
INPUT CAPTURE IN CPU SLEEP
MODE
INPUT CAPTURE IN CPU IDLE
MODE
capture
© 2008 Microchip Technology Inc.
module
is
defined
as