DSPIC30F6010AT-30I/PF Microchip Technology, DSPIC30F6010AT-30I/PF Datasheet - Page 107
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DSPIC30F6010AT-30I/PF
Manufacturer Part Number
DSPIC30F6010AT-30I/PF
Description
IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6011A-30IPT.pdf
(6 pages)
4.DSPIC30F6015-30IPT.pdf
(232 pages)
5.DSPIC30F6015-30IPT.pdf
(14 pages)
6.DSPIC30F6015-30IPT.pdf
(12 pages)
7.DSPIC30F6015-30IPT.pdf
(18 pages)
8.DSPIC30F6010A-30IPF.pdf
(22 pages)
Specifications of DSPIC30F6010AT-30I/PF
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010AT-30I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F6011A-30IPT PDF datasheet #3
- DSPIC30F6015-30IPT PDF datasheet #4
- DSPIC30F6015-30IPT PDF datasheet #5
- DSPIC30F6015-30IPT PDF datasheet #6
- DSPIC30F6015-30IPT PDF datasheet #7
- DSPIC30F6010A-30IPF PDF datasheet #8
- Current page: 107 of 232
- Download datasheet (4Mb)
16.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SSx pin to
perform the Frame Synchronization pulse (FSYNC)
function. The control bit SPIFSD determines whether
the SSx pin is an input or an output (i.e., whether the
module
Synchronization pulse). The frame pulse is an
active-high pulse for a single SPI clock cycle. When
Frame Synchronization is enabled, the data transmis-
sion starts only on the subsequent transmit edge of the
SPI clock.
16.3
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SSx
pin control enabled (SSEN = 1). When the SSx pin is
low, transmission and reception are enabled, and the
SDOx pin is driven. When SSx pin goes high, the SDOx
pin is no longer driven. Also, the SPI module is
re-synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MSb,
even if SSx had been de-asserted in the middle of a
transmit/receive.
© 2008 Microchip Technology Inc.
Framed SPI Support
Slave Select Synchronization
receives
or
generates
the
Frame
dsPIC30F6010A/6015
16.4
During Sleep mode, the SPI module is shut down. If
the CPU enters Sleep mode while an SPI transaction
is in progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by
entering or exiting Sleep mode.
16.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle.
If SPISIDL = 0, the module will continue to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module will stop when the CPU enters Idle mode.
SPI Operation During CPU Sleep
Mode
SPI Operation During CPU Idle
Mode
DS70150D-page 107
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