DSPIC30F5015-20E/PT Microchip Technology, DSPIC30F5015-20E/PT Datasheet - Page 231

• Manufacturer Part Number: DSPIC30F5015-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Requirements
Timing Specifications
Traps .................................................................................. 41
U
UART
© 2007 Microchip Technology Inc.
SPI Master Mode (CKE = 1) .................................... 201
SPI Slave Mode (CKE = 0) ...................................... 202
SPI Slave Mode (CKE = 1) ...................................... 203
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
TimerQ (QEI Module) External Clock ...................... 194
Timer1, 2, 3, 4, 5 External Clock .............................. 192
10-bit High-Speed A/D Conversion (CHPS = 01,
10-bit High-Speed A/D Conversion (CHPS = 01,
Input Capture ........................................................... 195
Band Gap Start-up Time Requirements ................... 191
CAN I/O Requirements ............................................ 209
CLKOUT and I/O Characteristics ............................. 189
CLKOUT and I/O Requirements .............................. 189
External Clock Requirements .................................. 185
Internal Clock Examples .......................................... 187
I
I
Motor Control PWM Requirements .......................... 197
Output Compare Requirements ............................... 195
PLL Clock ................................................................. 186
PLL Jitter .................................................................. 186
QEI External Clock Requirements ........................... 194
QEI Index Pulse Requirements ................................ 199
Quadrature Decoder Requirements ......................... 198
Reset, Watchdog Timer, Oscillator Start-up
Simple OC/PWM Mode Requirements .................... 196
SPI Master Mode (CKE = 0) Requirements ............. 200
SPI Master Mode (CKE = 1) Requirements ............. 201
SPI Slave Mode (CKE = 0) Requirements ............... 202
SPI Slave Mode (CKE = 1) Requirements ............... 203
Timer1 External Clock Requirements ...................... 192
Timer2 and Timer4 External Clock Requirements ... 193
Timer3 and Timer5 External Clock Requirements ... 193
10-bit High-Speed A/D ............................................. 210
10-bit High-Speed A/D Conversion Requirements .. 214
Hard and Soft ............................................................. 42
Sources ...................................................................... 41
Vectors ....................................................................... 42
Address Detect Mode .............................................. 119
Auto-Baud Support .................................................. 120
Baud Rate Generator (BRG) .................................... 119
Disabling .................................................................. 117
Enabling and Setup .................................................. 117
Loopback Mode ....................................................... 119
Module Overview ..................................................... 115
Operation During CPU Sleep and Idle Modes ......... 120
Receiving Data ......................................................... 118
2
2
C Bus Data Requirements (Master Mode) ............ 206
C Bus Data Requirements (Slave Mode) .............. 208
Not Tied to V
Not Tied to V
Tied to V
SIMSAM = 0, ASAM = 0, SSRC = 000) ........... 212
SIMSAM = 0, ASAM = 1, SSRC = 111,
SAMC = 00001) ............................................... 213
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 191
In 8-bit or 9-bit Data Mode ............................... 118
Interrupt ........................................................... 118
Receive Buffer (UxRXB) .................................. 118
DD
) ..................................................... 154
DD
DD
), Case 1 ................................. 154
), Case 2 ................................. 155
dsPIC30F6010A/6015
Unit ID Locations ............................................................. 147
Universal Asynchronous Receiver Transmitter
W
Wake-up from Sleep ........................................................ 147
Wake-up from Sleep and Idle ............................................ 43
Watchdog Timer (WDT) ........................................... 147, 158
WWW Address ................................................................ 231
WWW, On-Line Support ...................................................... 5
Z
16-bit Up/Down Position Counter Mode ............................ 88
Reception Error Handling ........................................ 118
Setting Up Data, Parity and Stop Bit Selections ...... 117
Transmitting Data .................................................... 117
UART1 Register Map .............................................. 121
UART2 Register Map .............................................. 121
Module (UART) ........................................................ 115
Enabling and Disabling ............................................ 158
Operation ................................................................. 158
Count Direction Status ............................................... 88
Error Checking ........................................................... 88
Framing Error (FERR) ..................................... 119
Idle Status ....................................................... 119
Parity Error (PERR) ......................................... 119
Receive Break ................................................. 119
Receive Buffer Overrun Error (OERR Bit) ....... 118
In 8-bit Data Mode ........................................... 117
In 9-bit Data Mode ........................................... 117
Interrupt ........................................................... 118
Transmit Break ................................................ 118
Transmit Buffer (UxTXB) ................................. 117
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