DSPIC30F3010-20E/ML Microchip Technology, DSPIC30F3010-20E/ML Datasheet - Page 9
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DSPIC30F3010-20E/ML
Manufacturer Part Number
DSPIC30F3010-20E/ML
Description
IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F3010-30ISO.pdf
(228 pages)
4.DSPIC30F3010-30ISO.pdf
(18 pages)
5.DSPIC30F3010-30ISO.pdf
(6 pages)
6.DSPIC30F3010-30ISO.pdf
(16 pages)
7.DSPIC30F3010-30ISO.pdf
(22 pages)
Specifications of DSPIC30F3010-20E/ML
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8. Module: CPU
© 2010 Microchip Technology Inc.
When a user executes a DISI #7, interrupts are
disabled for 7 + 1 cycles (7 + the DISI instruction
itself). In this case, the DISI instruction uses a
counter which counts down from 7 to 0. The coun-
ter is loaded with 7 at the end of the DISI
instruction.
If the user code executes another DISI on the
instruction cycle where the DISI counter has
become zero, the new DISI count is loaded, but the
DISI state machine does not properly re-engage
and continue to disable interrupts. At this point, all
interrupts are enabled. The next time the user code
executes a DISI instruction, the feature will act
normally and block interrupts.
In summary, it is only when a DISI execution is
coincident with the current DISI count = 0, that the
issue occurs. Executing a DISI instruction before
the DISI counter reaches zero will not produce
this error. In this case, the DISI counter is loaded
with the new value, and interrupts remain disabled
until the counter becomes zero.
Work around
When executing multiple DISI instructions within
the source code, make sure that subsequent DISI
instructions have at least one instruction cycle
between the time that the DISI counter
decrements to zero and the next DISI instruction.
Alternatively, make sure that subsequent DISI
instructions are called before the DISI counter
decrements to zero.
Affected Silicon Revisions
A0
X
A1
X
A2
X
9. Module: 32 kHz Low-Power (LP)
10. Module: Output Compare
The LP oscillator is located on the SOSCO and
SOSCI device pins and serves as a secondary
crystal clock source for low-power operation. The
LP oscillator can also drive Timer1 for a real-time
clock application. The LP oscillator does not
function when the device is placed in Sleep mode.
Work around
No work around exists for this errata. However, if
the application needs to wake-up periodically from
Sleep mode using an internal timer, the Watchdog
Timer may be enabled prior to entering Sleep
mode. When the Watchdog Timer expires, code
execution will resume from the instruction
immediately following the SLEEP instruction.
Affected Silicon Revisions
If the desired duty cycle is 0 (OCxRS = 0), the
module will generate a high level glitch of 1 T
resulting issue is that on the next cycle after the
glitch, the OC pin does not go high, or, in other
words, it misses the next compare for any value
written on OCxRS.
Work around
There are two possible solutions to this issue:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
Affected Silicon Revisions
A0
A0
X
X
register when operating in PWM mode. In this
case, no 0% duty cycle is achievable.
output compare module can be disabled
for 0% duty cycles, and re-enabled for non-
zero percent duty cycles.
A1
A1
dsPIC30F3010/3011
X
X
Oscillator
A2
A2
X
X
DS80449D-page 9
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