DSPIC30F3010-20E/ML Microchip Technology, DSPIC30F3010-20E/ML Datasheet - Page 4
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DSPIC30F3010-20E/ML
Manufacturer Part Number
DSPIC30F3010-20E/ML
Description
IC,DSP,16-BIT,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F3010-30ISO.pdf
(228 pages)
4.DSPIC30F3010-30ISO.pdf
(18 pages)
5.DSPIC30F3010-30ISO.pdf
(6 pages)
6.DSPIC30F3010-30ISO.pdf
(16 pages)
7.DSPIC30F3010-30ISO.pdf
(22 pages)
Specifications of DSPIC30F3010-20E/ML
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
dsPIC30F3010/3011
Silicon Errata Issues
1. Module: CPU
DS80449D-page 4
Note:
Sequential MAC class instructions, which prefetch
data from Y data space using ±4 address
modification, will cause an address error trap. The
trap occurs only when all of the following
conditions are true:
1. Two sequential MAC class instructions (or a
2. Both instructions prefetch data from Y data
3. Neither of the instructions uses an accumulator
Work around
The problem described above can be avoided by
using any of the following methods:
1. Inserting any other instruction between the two
2. Adding an accumulator write back (a dummy
3. Do not use the + = 4 or - = 4 address
4. Do not prefetch data from Y data space.
Affected Silicon Revisions
A0
X
MAC class instruction executed in a REPEAT or
DO loop) that prefetch from Y data space.
space using the + = 4 or - = 4 address
modification.
write back.
MAC class instructions.
write back if needed) to either of the MAC class
instructions.
modification.
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
A1
X
A2
X
2. Module: CPU
EXAMPLE 1:
L0:DAW.b
L1: ....
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>), when
executed.
Work around
Check the Carry bit status prior to executing the
DAW.b instruction. If the Carry bit is set, set the
Carry bit again after executing the DAW.b
instruction. Example 1 shows how the application
should process the Carry bit during a BCD addition
operation.
Affected Silicon Revisions
.include “p30fxxxx.inc”
.......
MOV.b
MOV.b
ADD.b
BRA
DAW.b
BSET.b
BRA
A0
X
A1
X
#0x80, w0
#0x80, w1
w0, w1, w2 ;Perform addition
NC, L0
w2
L1
w2
SR, #C
A2
X
CHECK CARRY BIT BEFORE
DAW.b
© 2010 Microchip Technology Inc.
;First BCD number
;Second BCD number
;If C set go to L0
;If not,do DAW and
;set the carry bit
;and exit