CS61584A-IQ5Z Cirrus Logic Inc, CS61584A-IQ5Z Datasheet - Page 31

• Manufacturer Part Number: CS61584A-IQ5Z
• Description: IC,Line Interface,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IQ5Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3
Parallel port operation in Host mode is selected
when the MODE and P/S pins are set high. In this
mode, the CS61584A register set is accessed using
an 8-bit, multiplexed bi-directional address/data
bus AD[7:0]. Timing over the serial port is inde-
pendent of the transmit and receive system timing.
The device is compatible with both Intel and Mo-
torola bus formats. The Intel bus format is selected
when the BTS pin is low and the Motorola bus for-
mat is selected when the BTS pin is high. A read or
write is initiated by writing an address byte to
AD[7:0]. The device latches the address on the fall-
ing edge of ALE(AS). During a read cycle, the reg-
ister data is output during the later portion of the
RD or DS pulses. The read cycle is terminated and
the bus returns to a high impedance state as RD
transitions high in Intel timing or DS transitions
low in Motorola timing. During a write cycle, valid
write data must be present and held stable during
the later portion of the WR or DS pulses. A second
address byte is required when reading or writing
the Arbitrary Waveform registers (see below).
A read or write over the parallel port is initiated by
writing an address byte to AD[7:0]. The address
byte consists of two nibbles. The four most signifi-
cant bits AD[7:4] select one of 16 CS61584A de-
vices in the application. This device address value
is established by the SAD[7:4] pins. The four least
significant bits AD[3:0] are the register address for
the selected device, ranging from 0x00 to 0x09.
The first eight device registers are addressed from
0x00 to 0x07 in the four least significant bits of the
address. Because Arbitrary Waveform registers
0x08 and 0x09 access multiple bytes of RAM,
reading or writing these registers requires an addi-
tional RAM address byte for each data transfer.
The RAM address is an 8-bit, unsigned binary
number in the range of 0x00 to 0x29 to identify one
of 42 RAM locations. The data byte containing the
7-bit, 2’s complement number specifying the phase
DS261PP5
DS261F1
Parallel Port Operation
DS261PP5
amplitude completes a write cycle. The sequence
for writing to RAM is: first ALE(AS) addresses the
device, a second ALE(AS) addresses the RAM,
then a RD or WR (R/W) accesses the RAM data.
10. JTAG BOUNDARY SCAN
Board testing is supported through JTAG boundary
scan. Using boundary scan, the integrity of the dig-
ital paths between devices on a circuit board can be
verified. This verification is supported by the abil-
ity to externally set the signals on the digital output
pins of the CS61584A, and to externally read the
signals present on the input pins of the CS61584A.
Additionally, the manufacturer ID, part number
and revision of the device can be read during board
test using JTAG boundary scan.
As shown in Figure 23, the JTAG hardware con-
sists of data and instruction registers plus a Test
Access Port (TAP) controller. Control of the TAP
is achieved through signals applied to the Test
Mode Select (J-TMS) and Test Clock (J-TCK) in-
put pins. Data is shifted into the registers via the
Test Data Input (J-TDI) pin, and shifted out of the
registers via the Test Data Output (J-TDO) pin.
Both J-TDI and J-TDO are clocked at a rate deter-
mined by J-TCK. The Instruction register defines
which data register is accessed in the shift opera-
tion. Note that if J-TDI is floating, an internal pull-
up resistor forces the pin high.
J-TMS
J-TCK
J-TDI
Figure 23. JTAG Circuitry Block Diagram
Digital output pins
parallel latched
parallel latched
Boundary Scan Data Register
Controller
Instruction (shift) Register
Device ID Data Register
TAP
output
output
Bypass Data Register
Digital input pins
CS61584A
CS61584A
JTAG Block
MUX
J-TDO
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