CS61584A-IQ5Z Cirrus Logic Inc, CS61584A-IQ5Z Datasheet

CS61584A-IQ5Z

Manufacturer Part Number

CS61584A-IQ5Z

Description

IC,Line Interface,QFP,64PIN,PLASTIC

Manufacturer

Cirrus Logic Inc

Datasheets

1.CS61584A.pdf (54 pages)

2.CS61584A-IQ5Z.pdf (54 pages)

Specifications of CS61584A-IQ5Z

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Features

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760

http://www.cirrus.com

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

Dual T1/E1 Line Interface

3.3 Volt and 5 Volt Versions

Crystal-less Jitter Attenuator Meets

European CTR 12 and ETSI ETS 300 011

Specifications

Matched Impedance Transmit Drivers

Transmitter Tri-state Capability

Common Transmit and

ReceiveTransformers for all Modes

Serial and Parallel Host Mode Operation

User-customizable Pulse Shapes

Supports JTAG Boundary Scan

Compliant with:

– ITU-T Recommendations: G.703, G.704,

– American National Standards (ANSI): T1.102,

– FCC Rules and Regulations: Part 68 and Part

G.706, G.732, G.775 and I.431

T1.105, T1.403, T1.408, and T1.231

(RDATA1) RPOS1

(RDATA2) RPOS2

(TDATA1) TPOS1

(TDATA2) TPOS2

Hardware Mode

(BPV1) RNEG1

(BPV2) RNEG2

(AIS1) TNEG1

(AIS2) TNEG2

Parallel Port

Serial Port

RCLK1

RCLK2

TCLK1

TCLK2

IPOL (DTACK)

CLKE

IPOL

JTAG

Dual T1/E1 Line Interface

ATTEN0

Dual T1/E1 Line Interface

P/S

REFCLK

ATTEN1

CLOCK GENERATOR

XTALOUT

RLOOP1

INT

ATTENUATOR

JITTER

RLOOP2

RD(DS)

SCLK

1XCLK

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

LLOOP

SDO

AD0

TV+ TGND RV+ RGND DV+ DGND

TAOS1

AD1

SDI

Cirrus Logic, Inc. 2005

TAOS2

SPOL

AD2

DETECT

CONTROL

TAOS

LOS &

TAOS

LOS &

AIS

CON01

AD3

Description

The CS61584A is a dual line interface for T1/E1 appli-

cations, designed for high-volume cards where low

power and high density are required. The device is op-

timized for flexible microprocessor control through a

serial or parallel Host mode interface. Hardware mode

operation is also available.

Matched impedance drivers reduce power consumption

and provide substantial transmitter return loss. The

transmitter pulse shapes are customizable to allow non-

standard line loads. Crystalless jitter attenuation com-

plies with most stringent standards. Support of JTAG

boundary scan enhances system testability and

reliability.

ORDERING INFORMATION

– AT&T Publication 62411

– ETSI ETS 300 011, 300 233, CTR 12, TBR 13

TR-NET-00499

CON02

CIRCUITRY

RECOVERY

CIRCUITRY

RECOVERY

SHAPING

CLOCK &

SHAPING

CLOCK &

AD4

PULSE

See

CS61584A-IQ3:3.3V, 64-pin TQFP, -40 to +85° C

CS61584A-IL5:5.0V, 68-pin PLCC, -40 to +85° C

CS61584A-IQ5:5.0V, 64-pin TQFP, -40 to +85° C

DATA

Cirrus Logic, Inc. 2000

CON11

AD5

AV+ AGND BGREF

page

CON12

AD6

DRIVER

RECEIVER

53.

CON21

AD7

SAD4

ZTX1

PD1

ALE(AS)

CON22

SAD5

ZTX2

PD2

CONTROL

WR(R/W)

CON31

LOS1

SAD6

LOS1

CON32

LOS2

SAD7

LOS2

BTS

CS61584A

TTIP1

TTIP2

Hardware Mode

Parallel Port

Serial Port

TRING1

RTIP1

TRING2

RTIP2

RRING1

RRING2

RESET

MODE

DS261PP5

DS261F1

JAN ‘01

SEP ‘05

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