CS61584A-IQ5Z Cirrus Logic Inc, CS61584A-IQ5Z Datasheet - Page 19

• Manufacturer Part Number: CS61584A-IQ5Z
• Description: IC,Line Interface,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IQ5Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the CLKE pin determines the clock polarity where
the output data is stable and valid as shown in
Table 2. During Host mode operation, the polarity
is established by the CLKE bit in the Control A reg-
ister. When CLKE is low, RPOS and RNEG (or
RDATA) are valid on the rising edge of RCLK.
When CLKE is high, RPOS and RNEG (or RDA-
TA) are valid on the falling edge of RCLK
During Host mode operation, the data at RPOS and
RNEG (or RDATA) may be forced to output an un-
framed all-ones pattern by setting both the
LLOOP1 and LLOOP2 bits in the Control B regis-
ter to "1".
5. JITTER ATTENUATOR
The jitter attenuator can be switched into either the
receive or transmit paths. Alternatively, it can also
be removed from both paths to reduce the propaga-
tion delay. Figure 14 illustrates the typical jitter at-
tenuation curves.
DS261PP5
DS261F1
LOW
HIGH
CLKE
10
20
30
40
50
60
Figure 17. Typical Jitter Transfer Function
0
Table 2. Recovered Data/Clock Options
1
RPOS, RNEG
RPOS, RNEG
Maximum
Attenuation
Limit
or RDATA
or RDATA
DATA
E1 Mode
10
Minimum Attenuation Limit
Frequency in Hz
100
CLOCK Clock edge for
RCLK
RCLK
RCLK
RCLK
62411 Requirements
Measured Performance
1 k
T1 Mode
valid data
Falling
Falling
Rising
Rising
10 k
DS261PP5
During Hardware mode operation, the location of
the jitter attenuators for both channels is controlled
by the ATTEN0 and ATTEN1 pins. During Host
mode operation, the location of the jitter attenua-
tors are independent and are controlled by the AT-
TEN[1:0] bits in the Control A registers. Table 3
shows how these pins are decoded.
The attenuator consists of a 64-bit FIFO, a narrow-
band monolithic PLL, and control logic. Signal jit-
ter is absorbed in the FIFO which is designed to
neither overflow nor underflow. If overflow or un-
derflow is imminent, the jitter transfer function is
altered to ensure that no bit-errors occur. Under this
condition, jitter gain may occur and external provi-
sions may be required. The jitter attenuator will
typically tolerate 43 UIs before the overflow/un-
derflow mechanism occurs. If the jitter attenuator
has not had time to "lock" to the average incoming
frequency (e.g. following a device reset) the atten-
uator will tolerate a minimum of 22 UIs before the
overflow/underflow mechanism occurs.
The jitter attenuator -3 dB knee frequency is 4.0 Hz
for T1 mode and 1.25 Hz for E1 mode as selected
by the CON[3:0] pins or register bits. A 1.25 Hz
knee for the E1 mode guarantees jitter attenuation
compliance to European specifications CTR 12 and
ETSI ETS 300 011. Setting ATTEN[1:0] = 11 will
place the jitter attenuator in the receive path with a
1.25 Hz knee for both T1 and E1 modes of opera-
tion.
For T1/E1 line cards used in high-speed mutiplex-
ers (e.g., SONET and SDH), the jitter attenuator is
typically used in the transmit path. The attenuator
can accept a transmit clock with gaps 28 UIs and
a transmit clock burst rate of
ATTEN1 ATTEN0
0
0
1
1
Table 3. Jitter Attenuation Control
0
1
0
1
Location of Jitter Attenuator
Receiver w/ 1.25 Hz knee
Transmitter
Receiver
Disabled
8 MHz.
CS61584A
CS61584A
19
19