P89LPC938FDH NXP Semiconductors, P89LPC938FDH Datasheet - Page 17

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P89LPC938FDH

Manufacturer Part Number
P89LPC938FDH
Description
MCU 8BIT 80C51 8K FLASH, TSSOP28
Manufacturer
NXP Semiconductors
Datasheet

Specifications of P89LPC938FDH

Controller Family/series
(8051) 8052
Core Size
8bit
No. Of I/o's
26
Program Memory Size
8KB
Eeprom Memory Size
512Byte
Ram Memory Size
768Byte
Cpu Speed
18MHz
Oscillator Type
External,
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 4:
* indicates SFRs that are bit addressable.
[1]
[2]
[3]
[4]
[5]
[6]
Name
WDL
WFEED1
WFEED2
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
All ports are in input only (high-impedance) state after power-up.
The RSTSRC register reflects the cause of the P89LPC938 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx110000.
The only reset source that affects these SFRs is power-on reset.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
After reset, the value is 111001x1, i.e., PRE2-PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
P89LPC938 Special function registers
Description
Watchdog load
Watchdog feed 1
Watchdog feed 2
SFR
addr.
C1H
C2H
C3H
Bit functions and addresses
…continued
MSB
LSB
Reset value
Hex
FF
Binary
11111111

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