P89LPC9103FTK NXP Semiconductors, P89LPC9103FTK Datasheet - Page 40

• Manufacturer Part Number: P89LPC9103FTK
• Description: MCU 8BIT 80C51 1K FLASH, HVSON-10
• Manufacturer: NXP Semiconductors

Specifications of P89LPC9103FTK

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 8
• Program Memory Size: 1KB
• Ram Memory Size: 128Byte
• Cpu Speed: 18MHz
• Oscillator Type: Internal Only
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant

NXP Semiconductors
P89LPC9102_9103_9107_3
Product data sheet
Fig 17. Watchdog timer in Watchdog mode (WDTE = 1)
(1) Watchdog timer reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by
a feed sequence.
watchdog
oscillator
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
PCLK
8.25.1 Software reset
8.25.2 Dual data pointers
8.25 Additional features
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog timer feature is disabled, it can be used as an interval
timer and may generate an interrupt.
mode. Feeding the watchdog timer requires a two-byte sequence. If PCLK is selected as
the watchdog timer clock and the CPU is powered-down, the watchdog timer is disabled.
The watchdog timer has a time-out period that ranges from a few s to a few seconds.
Please refer to the P89LPC9102/9103/9107 User manual UM10112 for more details.
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog timer reset had occurred. Care should be taken when
writing to AUXR1 to avoid accidental software resets.
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
WDCON (A7H)
32
PRE2
PRESCALER
PRE1
Rev. 03 — 10 July 2007
8-bit microcontrollers with two-clock accelerated 80C51 core
PRE0
SHADOW REGISTER
Figure 17
-
P89LPC9102/9103/9107
-
8-BIT DOWN
shows the watchdog timer in Watchdog
WDL (C1H)
COUNTER
WDRUN
WDTOF
WDCLK
© NXP B.V. 2007. All rights reserved.
002aaa980
reset (1)
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