AC80566UC005DE S LB2C Intel, AC80566UC005DE S LB2C Datasheet - Page 15

• Manufacturer Part Number: AC80566UC005DE S LB2C
• Description: MPU, ATOM PROCESSOR, Z510, U-FCBGA
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of AC80566UC005DE S LB2C

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 400MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 441
• Supply Voltage Range: 0.75V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low Power Features
2.1.1
2.1.1.1
2.1.1.1.1
Datasheet
Table 2. Coordination of Thread Low-Power States at the Package/Core Level
NOTE: AutoHalt or MWAIT/C1
To enter a package/core state, both threads must share a common low power state. If
the threads are not in a common low power state, the package state will resolve to
the highest common power C-state.
Package/Core Low-Power State Descriptions
The following state descriptions assume that both threads are in a common low power
state. For cases when only one thread is in a low power state no change in power
state will occur.
Normal States (C0, C1)
These are the normal operating states for the processor. The processor remains in the
Normal state when the processor/core is in the C0, C1/AutoHALT, or C1/MWAIT
states. C0 is the active execution state.
C1/AutoHalt Powerdown State
C1/AutoHALT is a low-power state entered when one thread executes the HALT
instruction while the other is in the TC1 or greater thread state. The processor will
transition to the C0 state upon occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or
FSB interrupt messages. RESET# will cause the processor to immediately initialize
itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures
Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more
information.
The system can generate a STPCLK# while the processor is in the AutoHALT
Powerdown state. When the system de-asserts the STPCLK# interrupt, the processor
will return to the HALT state.
While in AutoHALT Powerdown state, the processor will process bus snoops. The
processor will enter an internal snoopable sub-state (not shown in Figure 1) to process
the snoop and then return to the AutoHALT Powerdown state.
Thread 1
TC4/TC6
TC1
TC0
TC2
Thread 0
1
Normal (C0)
Normal (C0)
Normal (C0)
Normal (C0)
TC0
AutoHalt (C1)
AutoHalt (C1)
AutoHalt (C1)
Normal (C0)
TC1
1
Stop-Grant (C2)
Stop-Grant (C2)
AutoHalt (C1)
Normal (C0)
TC2
(C4)/Deep Power
Stop-Grant (C2)
AutoHalt (C1)
Deeper Sleep
Normal (C0)
Down (C6)
TC4/TC6
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