AC80566UC005DE S LB2C Intel, AC80566UC005DE S LB2C Datasheet - Page 14

• Manufacturer Part Number: AC80566UC005DE S LB2C
• Description: MPU, ATOM PROCESSOR, Z510, U-FCBGA
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of AC80566UC005DE S LB2C

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 400MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 441
• Supply Voltage Range: 0.75V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14
Figure 1. Thread Low-Power States
Figure 2. Package Low-Power States
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
† — STPCLK# assertion and de-assertion have no effect if a core is in C2 or C4.
Ø — P_LVL6 read is issued once the L2 cache is reduced to zero.
† — Deeper Sleep includes the C4 and C6 states
†† — Sleep and Deep Sleep are not states directly supported by the processor, but rather sub-states of Silverthorne’s C4/C6
Normal
MWAIT
STPCLK# de-asserted
STPCLK# asserted
C1/
C4
†
/
C6
serviced
Snoop
MWAIT(C1)
STPCLK#
Snoop
Grant
Grant
asserted
Stop
Stop
Core State
break
de-asserted
Core state
Snoop
occurs
MWAIT(C4/C6)
STPCLK#
break
P_LVL4 or
P_LVL6
SLP# de-asserted
SLP# asserted
ø
STPCLK#
asserted
Grant
Stop
Sleep
C0
de-asserted
STPCLK#
††
DPSLP# de-asserted
DPSLP# asserted
HLT instruction
STPCLK#
asserted
Core state
de-asserted
Halt break
STPCLK#
MWAIT(C2)
break
P_LVL2 or
Sleep
Deep
††
Low Power Features
DPRSTP# de-asserted
DPRSTP# asserted
C1/Auto
Halt
C2
†
Deeper
Datasheet
Sleep
†