NRF24L01G NORDIC SEMICONDUCTOR, NRF24L01G Datasheet - Page 51

• Manufacturer Part Number: NRF24L01G
• Description: IC, RF TRANSCEIVER, 2.4-2.4835GHZ QFN-20
• Manufacturer: NORDIC SEMICONDUCTOR

Specifications of NRF24L01G

• Transmitting Current: 11.3mA
• Data Rate: 2Mbps
• Frequency Range: 2.4GHz To 2.4835GHz
• Modulation Type: GFSK
• Sensitivity Dbm: -82dBm
• Rf Ic Case Style: QFN
• No. Of Pins: 20
• Sensitivity (dbm): -82dBm
• Supply Voltage Range: 1.9V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

nRF24L01 Product Specification
8.4
The data FIFOs are used to store payload that is transmitted (TX FIFO) or payload that is received and
ready to be clocked out (RX FIFO). The FIFOs are accessible in both PTX mode and PRX mode.
The following FIFOs are present in nRF24L01:
Both FIFOs have a controller and are accessible through the SPI by using dedicated SPI commands. A TX
FIFO in PRX can store payload for ACK packets to three different PTX devices. If the TX FIFO contains
more than one payload to a pipe, payloads are handled using the first in - first out principle. The TX FIFO in
a PRX is blocked if all pending payloads are addressed to pipes where the link to the PTX is lost. In this
case, the MCU can flush the TX FIFO by using the FLUSH_TX command.
The RX FIFO in PRX may contain payload from up to three different PTX devices.
A TX FIFO in PTX can have up to three payloads stored.
The TX FIFO can be written to by three commands, W_TX_PAYLOAD and W_TX_PAYLOAD_NO_ACK in PTX
mode and W_ACK_PAYLOAD in PRX mode. All three commands give access to the TX_PLD register.
The RX FIFO can be read by the command R_RX_PAYLOAD in both PTX and PRX mode. This command
gives access to the RX_PLD register.
The payload in TX FIFO in a PTX is NOT removed if the MAX_RT IRQ is asserted.
gram of the TX FIFO and the RX FIFO.
In the FIFO_STATUS register it is possible to read if the TX and RX FIFO is full or empty. The TX_REUSE
bit is also available in the FIFO_STATUS register. TX_REUSE is set by the SPI command REUSE_TX_PL,
and is reset by the SPI commands W_TX_PAYLOAD or FLUSH TX.
Revision 2.0
•
•
TX three level, 32 byte FIFO
RX three level, 32 byte FIFO
Data FIFO
Data
Data
Figure 27. FIFO block diagram
RX FIFO Controller
TX FIFO Controller
RX FIFO
TX FIFO
32 byte
32 byte
32 byte
32 byte
32 byte
32 byte
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Control
Control
Data
Data
command
decoder
SPI
Figure 27.
is a block dia-