PIC32MX795F512L-80I/BG Microchip Technology, PIC32MX795F512L-80I/BG Datasheet - Page 13
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PIC32MX795F512L-80I/BG
Manufacturer Part Number
PIC32MX795F512L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX795F512L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
128KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
CAN, I2C, SPI, UART, USB
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
512 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX7xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX795F512L-80I/BG
Manufacturer:
Microchip
Quantity:
316
Company:
Part Number:
PIC32MX795F512L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
6.4
Format:
Purpose:
Description (in sequence):
1.
2.
FIGURE 6-7:
FIGURE 6-8:
© 2010 Microchip Technology Inc.
TMS
TDO
oData = XferFastData (iData)
To quickly send 32 bits of data in/out of the device.
TCK
Note:
Note:
TDI
PGC
PGD
The TMS Header is clocked into the device to
select the Shift DR state.
The input value of the PrAcc bit, which is ‘0’, is
clocked in.
XferFastData Pseudo Operation
For 2-wire (4-phase) – on the last clock,
the oPrAcc bit is shifted out on TDO while
clocking in the TMS Header. If the value of
oPrAcc is not ‘1’, the whole operation must
be repeated.
For 2-wire (4-phase) – the TDO during this
operation will be the LSb of output data.
The rest of the 31 bits of the input data are
clocked in and the 31 bits of output data
are clocked out. For the last bit of the input
data, the TMS Footer = 1 is set.
TDI =
TMS Header = 100
‘1’
X
TMS Header = 100
TMS = 1
‘0’
XferFastData 4-WIRE
XferFastData 2-WIRE (2-PHASE)
‘0’
TDI = 0
PrAcc
PrAcc
TMS = 0
‘0’
‘1’
TDO =
iLSb
oLSb
iLSb
Data (32’h12)
TMS = 0
Data (32’h12)
3.
Restrictions:
EXAMPLE 6-1:
// Select the Fastdata Register
SendCommand(ETAP_FASTDATA)
// Send/Receive 32-bit Data
oData = XferFastData(32’h12)
The SendCommand (ETAP_FASTDATA) must be sent
first to select the Fastdata register, as shown in
Example 6-1. See Table 19-4 for a detailed descriptions
of commands.
Note:
TMS Footer = 10 is clocked in to return the TAP
controller to the Run/Test Idle state.
The 2-Phase XferData is only used when
talking to the PE. See 16.0 “The Pro-
gramming
information.
Data (MSb) +
Data (MSb) TMS = 1
TDI =
TMS = 1
MSb
oMSb
iMSb
‘1’
TMS = 1
SendCommand
Executive”
‘1’
TDI =
TMS Footer = 10
PIC32MX
TMS Footer = 10
X
TMS = 1
DS61145G-page 13
‘0’
for
more