LPC2364FBD100 NXP Semiconductors, LPC2364FBD100 Datasheet - Page 28

• Manufacturer Part Number: LPC2364FBD100
• Description: IC, 32BIT MCU, ARM7, 72MHZ, LQFP-100
• Manufacturer: NXP Semiconductors

Specifications of LPC2364FBD100

• Controller Family/series: (ARM7)
• No. Of I/o's: 70
• Ram Memory Size: 34KB
• Cpu Speed: 72MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 6
• Core Size: 32 Bit
• Program Memory Size: 128KB
• Embedded Interface Type: CAN, SPI, USB, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC2364_65_66_67_68_6
Product data sheet
7.21.1 Features
7.22.1 Features
7.22 Watchdog timer
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the PWMMR0 match register controls the PWM cycle rate. The other match
registers control the two PWM edge positions. Additional double edge controlled PWM
outputs require only two match registers each, since the repetition rate is the same for all
PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
•
•
•
•
•
•
•
•
•
•
•
LPC2364/65/66/67/68 has one PWM block with Counter or Timer operation (may use
the peripheral clock or one of the capture inputs as the clock source).
Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Rev. 06 — 1 February 2010
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
© NXP B.V. 2010. All rights reserved.
28 of 59