LPC2364FBD100 NXP Semiconductors, LPC2364FBD100 Datasheet - Page 25

• Manufacturer Part Number: LPC2364FBD100
• Description: IC, 32BIT MCU, ARM7, 72MHZ, LQFP-100
• Manufacturer: NXP Semiconductors

Specifications of LPC2364FBD100

• Controller Family/series: (ARM7)
• No. Of I/o's: 70
• Ram Memory Size: 34KB
• Cpu Speed: 72MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 6
• Core Size: 32 Bit
• Program Memory Size: 128KB
• Embedded Interface Type: CAN, SPI, USB, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC2364_65_66_67_68_6
Product data sheet
7.16.1 Features
7.17.1 Features
7.16 SSP serial I/O controller
7.17 SD/MMC card interface (LPC2367/68 only)
7.18 I
The LPC2364/65/66/67/68 each contain two SSP controllers. The SSP controller is
capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple
masters and slaves on the bus. Only a single master and a single slave can communicate
on the bus during a given data transfer. The SSP supports full duplex transfers, with
frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave
to the master. In practice, often only one of these data flows carries meaningful data.
The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD
memory cards. The SD card interface conforms to the SD Multimedia Card Specification
Version 2.11.
The LPC2364/65/66/67/68 each contain three I
The I
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
(Fast I
2
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C-bus serial I/O controllers
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
The MCI interface provides all functions specific to the SD/MMC memory card. These
include the clock generation unit, power management control, and command and data
transfer.
Conforms to Multimedia Card Specification v2.11.
Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.
Can be used as a multimedia card bus or a secure digital memory card bus host. The
SD/MMC can be connected to several multimedia cards or a single secure digital
memory card.
DMA supported through the GPDMA controller.
2
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
C-bus implemented in LPC2364/65/66/67/68 supports bit rates up to 400 kbit/s
2
C-bus).
Rev. 06 — 1 February 2010
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
2
C-bus controllers.
2
C is a multi-master bus, it can be
© NXP B.V. 2010. All rights reserved.
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