HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 406

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
19.3
19.3.1
Figure 19.3 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the internal pull-up resistor (Typ. 150 kΩ). While the RES signal is driven low, the prescaler S and
the entire chip retains the reset state. When the level on the RES signal reaches the specified value,
the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to
release the internal reset signal after the prescaler S has counted 131,072 cycles of the φ clock. The
noise filter circuit which removes noise with less than 400 ns (Typ.) is included to prevent the
incorrect operation of this LSI caused by noise on the RES signal.
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle
(t
pin (C
power supply, the power supply circuit should be designed to satisfy the following formula.
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV to remove charge on the
RES pin. After that, it can be risen. To remove charge on the RES pin, it is recommended that the
diode should be placed to Vcc. If the power supply voltage (Vcc) rises from the point above Vpor,
a power-on reset may not occur.
Rev. 1.00 Sep. 16, 2005 Page 376 of 490
REJ09B0216-0100
PWON
) is determined by the oscillation frequency (f
RES
t
). Where t
PWON
Operations
Power-On Reset Circuit
(t
(ms) ≤ 90 × C
PWON
≤ 3000 ms, C
PWON
is assumed to be the time required to reach 90 % of the full level of the
RES
(µF) + 162/f
RES
≥ 0.22 µF, and f
OSC
(MHz)
OSC
OSC
) and capacitance which is connected to RES
= 10 in 2-MHz to 10-MHz operation)