HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 24

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 16.18 Example of SCI3 Reception Using Multiprocessor Format
Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 319
Section 17 I
Figure 17.1 Block Diagram of I
Figure 17.2 External Circuit Connections of I/O Pins ................................................................ 323
Figure 17.3 I
Figure 17.4 I
Figure 17.5 Master Transmit Mode Operation Timing (1)......................................................... 339
Figure 17.6 Master Transmit Mode Operation Timing (2)......................................................... 339
Figure 17.7 Master Receive Mode Operation Timing (1) .......................................................... 341
Figure 17.8 Master Receive Mode Operation Timing (2) .......................................................... 342
Figure 17.9 Slave Transmit Mode Operation Timing (1) ........................................................... 343
Figure 17.10 Slave Transmit Mode Operation Timing (2) ......................................................... 344
Figure 17.11 Slave Receive Mode Operation Timing (1)........................................................... 345
Figure 17.12 Slave Receive Mode Operation Timing (2)........................................................... 345
Figure 17.13 Clock Synchronous Serial Transfer Format .......................................................... 346
Figure 17.14 Transmit Mode Operation Timing......................................................................... 347
Figure 17.15 Receive Mode Operation Timing .......................................................................... 348
Figure 17.16 Block Diagram of Noise Filter .............................................................................. 349
Figure 17.17 Sample Flowchart for Master Transmit Mode ...................................................... 350
Figure 17.18 Sample Flowchart for Master Receive Mode ........................................................ 351
Figure 17.19 Sample Flowchart for Slave Transmit Mode......................................................... 352
Figure 17.20 Sample Flowchart for Slave Receive Mode .......................................................... 353
Figure 17.21 The Timing of the Bit Synchronous Circuit .......................................................... 355
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 358
Figure 18.2 A/D Conversion Timing.......................................................................................... 364
Figure 18.3 External Trigger Input Timing ................................................................................ 365
Figure 18.4 A/D Conversion Accuracy Definitions (1).............................................................. 367
Figure 18.5 A/D Conversion Accuracy Definitions (2).............................................................. 367
Figure 18.6 Analog Input Circuit Example ................................................................................ 368
Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
Figure 19.1 Block Diagram around BGR ................................................................................... 370
Figure 19.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 371
Figure 19.3 Operational Timing of Power-On Reset Circuit...................................................... 377
Figure 19.4 Operating Timing of LVDR Circuit ........................................................................ 378
Figure 19.5 Operational Timing of LVDI Circuit ...................................................................... 379
Rev. 1.00 Sep. 16, 2005 Page xxiv of xxx
2
2
2
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 316
C Bus Interface 2 (IIC2)
C Bus Formats ...................................................................................................... 337
C Bus Timing........................................................................................................ 337
2
C Bus Interface 2..................................................................... 322