PIC16F1827-I/MQ Microchip Technology, PIC16F1827-I/MQ Datasheet - Page 96

• Manufacturer Part Number: PIC16F1827-I/MQ
• Description: IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
• Manufacturer: Microchip Technology

Specifications of PIC16F1827-I/MQ

• Controller Family/series: PIC16F
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 384Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Core Size: 8 Bit
• Program Memory Size: 4 Kwords
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 384 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN EP
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / Rohs Status: Details

PIC16F/LF1826/27
8.5.8
The PIR3 register contains the interrupt flag bits, as
shown in Register 8-8.
REGISTER 8-8:
DS41391B-page 96
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
This register is only available on PIC16F/LF1827.
PIR3 REGISTER
Unimplemented: Read as ‘0’
CCP4IF: CCP4 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
CCP3IF: CCP3 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
TMR6IF: TMR6 to PR6 Match Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
U-0
—
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
(1)
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
CCP4IF
R/W-0/0
CCP3IF
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
TMR6IF
Note 1: The PIR3 register is available only on the
2: Interrupt flag bits are set when an inter-
PIC16F/LF1827 device.
rupt condition occurs, regardless of the
state of its corresponding enable bit or the
Global Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
U-0
—
© 2009 Microchip Technology Inc.
(1)
R/W-0/0
TMR4IF
U-0
—
bit 0