PIC16F1827-I/MQ Microchip Technology, PIC16F1827-I/MQ Datasheet - Page 115

IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28

PIC16F1827-I/MQ

Manufacturer Part Number
PIC16F1827-I/MQ
Description
IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
Manufacturer
Microchip Technology
Datasheet

Specifications of PIC16F1827-I/MQ

Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
4 Kwords
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Program Memory Type
Flash
Data Ram Size
384 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
15
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN EP
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / Rohs Status
 Details
11.4
Instead of accessing program memory or EEPROM
data memory, the User ID’s, Device ID/Revision ID and
Configuration
CFGS = 1. This is the region that would be pointed to
by PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 11-1.
TABLE 11-1:
EXAMPLE 11-3:
© 2009 Microchip Technology Inc.
* This code block will read 1 word of program
* memory at the memory address:
*
*
PROG_ADDR_HI: PROG_ADDR_LO
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWL
BCF
BSF
BCF
BSF
NOP
NOP
BSF
MOVF
MOVWF
MOVF
MOVWF
Configuration Word and Device ID
Access
8000h-8003h
8007h-8008h
Address
8006h
EEADRL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
INTCON,GIE
EEDATL,W
PROG_DATA_LO
EEDATH,W
PROG_DATA_HI
Words
PFM AND FUSE ACCESS VIA EECON1/EEDATH:EEDATL REGISTERS
(WHEN CFGS = 1)
CONFIGURATION WORD AND DEVICE ID ACCESS
can
be
Configuration Words 1 and 2
Device ID/Revision ID
accessed
; Select Bank 2
;
; Store LSB of address
;
; Store MSB of address
; Deselect Configuration Space
; Select Program Memory
; Disable interrupts
; Initiate read
; Executed (Figure 11-1)
; Ignored (Figure 11-1)
; Restore interrupts
; Get LSB of word
; Store in user location
; Get MSB of word
; Store in user location
Function
User IDs
when
Preliminary
When read access is initiated on an unallowed
address, the EEDATH:EEDATL registers are cleared.
Writes can be disabled via the WRT Configuration bits.
Refer to the Configuration Word 2.
Read Access
PIC16F/LF1826/27
Yes
Yes
Yes
Write Access
DS41391B-page 115
Yes
No
No

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