PIC16F1827-I/MQ Microchip Technology, PIC16F1827-I/MQ Datasheet - Page 92
PIC16F1827-I/MQ
Manufacturer Part Number
PIC16F1827-I/MQ
Description
IC, 8BIT MCU, PIC16F, 32MHZ, QFN-28
Manufacturer
Microchip Technology
Datasheet
1.PIC16LF1827-ISS.pdf
(400 pages)
Specifications of PIC16F1827-I/MQ
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
4 Kwords
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Program Memory Type
Flash
Data Ram Size
384 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
15
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN EP
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / Rohs Status
Details
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PIC16F/LF1826/27
8.5.4
The PIE3 register contains the interrupt enable bits, as
shown in Register 8-4.
REGISTER 8-4:
DS41391B-page 92
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
This register is only available on PIC16F/LF1827.
PIE3 REGISTER
Unimplemented: Read as ‘0’
CCP4IE: CCP4 Interrupt Enable bit
1 = Enables the CCP4 interrupt
0 = Disables the CCP4 interrupt
CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the TMR6 to PR6 Match interrupt
0 = Disables the TMR6 to PR6 Match interrupt
Unimplemented: Read as ‘0’
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 Match interrupt
0 = Disables the TMR4 to PR4 Match interrupt
Unimplemented: Read as ‘0’
U-0
—
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
(1)
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
CCP4IE
R/W-0/0
CCP3IE
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
TMR6IE
R/W-0/0
Note 1: The PIE3 register is available only on the
2: Bit PEIE of the INTCON register must be
PIC16F/LF1827 device.
set to enable any peripheral interrupt.
U-0
—
© 2009 Microchip Technology Inc.
(1)
R/W-0/0
TMR4IE
U-0
—
bit 0
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