PIC12LF1822-I/MF Microchip Technology, PIC12LF1822-I/MF Datasheet - Page 82
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PIC12LF1822-I/MF
Manufacturer Part Number
PIC12LF1822-I/MF
Description
IC, 8BIT MCU, PIC12, 32MHZ, DFN-8
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheets
1.PIC12F1822T-ISN.pdf
(404 pages)
2.PIC12F1822T-ISN.pdf
(10 pages)
3.PIC12F1822-IMF.pdf
(398 pages)
Specifications of PIC12LF1822-I/MF
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
256Byte
Ram Memory Size
128Byte
Cpu Speed
32MHz
No. Of Timers
3
Core Size
8 Bit
Program Memory Size
3.5KB
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Processor Series
PIC12LF
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1822-I/MF
Manufacturer:
MICROCHIP
Quantity:
3 600
- Current page: 82 of 404
- Download datasheet (4Mb)
PIC12F/LF1822/PIC16F/LF1823
7.10
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset.
tions of these registers.
TABLE 7-3:
TABLE 7-4:
DS41413B-page 82
Power-on Reset
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset
WDT Wake-up from Sleep
Brown-out Reset
Interrupt Wake-up from Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
STKOVF STKUNF RMCLR
0
0
0
0
u
u
u
u
u
u
1
u
2: If a Status bit is not implemented, that bit will be read as ‘0’.
Table 7-3
Determining the Cause of a Reset
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
0
0
0
0
u
u
u
u
u
u
u
1
and
RESET STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR SPECIAL REGISTERS
Table 7-4
Condition
1
1
1
1
u
u
u
0
0
u
u
u
show the Reset condi-
RI
1
1
1
1
u
u
u
u
u
0
u
u
POR
0
0
0
u
u
u
u
u
u
u
u
u
Preliminary
BOR
x
x
x
0
u
u
u
u
u
u
u
u
TO
1
0
x
1
0
0
1
u
1
u
u
u
Program
PC + 1
Counter
PC + 1
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
PD
1
x
0
1
u
0
0
u
0
u
u
u
(1)
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
(2)
---1 1000
---u uuuu
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
Register
STATUS
2010 Microchip Technology Inc.
Condition
00-- 110x
uu-- 0uuu
uu-- 0uuu
uu-- uuuu
uu-- uuuu
00-- 11u0
uu-- uuuu
uu-- u0uu
1u-- uuuu
u1-- uuuu
Register
PCON
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