PIC12LF1822-I/MF Microchip Technology, PIC12LF1822-I/MF Datasheet - Page 282
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PIC12LF1822-I/MF
Manufacturer Part Number
PIC12LF1822-I/MF
Description
IC, 8BIT MCU, PIC12, 32MHZ, DFN-8
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheets
1.PIC12F1822T-ISN.pdf
(404 pages)
2.PIC12F1822T-ISN.pdf
(10 pages)
3.PIC12F1822-IMF.pdf
(398 pages)
Specifications of PIC12LF1822-I/MF
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
256Byte
Ram Memory Size
128Byte
Cpu Speed
32MHz
No. Of Timers
3
Core Size
8 Bit
Program Memory Size
3.5KB
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Processor Series
PIC12LF
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1822-I/MF
Manufacturer:
MICROCHIP
Quantity:
3 600
- Current page: 282 of 404
- Download datasheet (4Mb)
PIC12F/LF1822/PIC16F/LF1823
REGISTER 25-3:
DS41413B-page 282
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0/0
GCEN
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).
GCEN: General Call Enable bit (in I
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (in I
1 = Acknowledge was not received
0 = Acknowledge was received
ACKDT: Acknowledge Data bit (in I
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (in I
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (in I
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit (in I
SCK Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN: Repeated Start Condition Enabled bit (in I
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN: Start Condition Enabled bit (in I
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
ACKSTAT
R-0/0
Automatically cleared by hardware.
SSP1CON2: SSP1 CONTROL REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
ACKDT
R/S/HS-0/0
2
ACKEN
2
C Master mode only)
C
Preliminary
2
2
2
C mode only)
C Slave mode only)
C Master mode only)
2
C Master mode only)
2
C mode only)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware
R/S/HS-0/0
2
RCEN
C module is not in the Idle mode, this bit may not be
2
2
C Master mode only)
C Master mode only)
R/S/HS-0/0
PEN
2010 Microchip Technology Inc.
S = User set
R/S/HS-0/0
RSEN
R/W/HS-0/0
SEN
bit 0
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