PIC12LF1822-I/MF Microchip Technology, PIC12LF1822-I/MF Datasheet - Page 327
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PIC12LF1822-I/MF
Manufacturer Part Number
PIC12LF1822-I/MF
Description
IC, 8BIT MCU, PIC12, 32MHZ, DFN-8
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheets
1.PIC12F1822T-ISN.pdf
(404 pages)
2.PIC12F1822T-ISN.pdf
(10 pages)
3.PIC12F1822-IMF.pdf
(398 pages)
Specifications of PIC12LF1822-I/MF
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
256Byte
Ram Memory Size
128Byte
Cpu Speed
32MHz
No. Of Timers
3
Core Size
8 Bit
Program Memory Size
3.5KB
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Processor Series
PIC12LF
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1822-I/MF
Manufacturer:
MICROCHIP
Quantity:
3 600
- Current page: 327 of 404
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29.0
Each PIC16 instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most var-
ied instruction word format.
Table 29-3
MPASM
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
• Program branching takes two cycles (GOTO, BRA,
• One additional instruction cycle will be used when
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
2010 Microchip Technology Inc.
cycles (RETURN, RETLW, RETFIE)
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
any instruction references an indirect file register
and the file select register is pointing to program
memory.
TM
INSTRUCTION SET SUMMARY
assembler.
lists the instructions recognized by the
PIC12F/LF1822/PIC16F/LF1823
Preliminary
29.1
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
TABLE 29-1:
TABLE 29-2:
Field
Field
mm
DC
PC
TO
PD
W
C
b
d
n
Z
k
x
f
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
Destination select; d = 0: store result in
d = 1: store result in file register f.
Default is d = 1.
FSR or INDF number. (0-1)
Pre-post increment-decrement mode
selection
Program Counter
Time-out bit
Carry bit
Digit carry bit
Zero bit
Power-down bit
Read-Modify-Write Operations
OPCODE FIELD
DESCRIPTIONS
ABBREVIATION
DESCRIPTIONS
Description
Description
DS41413B-page 327
W
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