LH79524N0F100A1;55 NXP Semiconductors, LH79524N0F100A1;55 Datasheet - Page 31

• Manufacturer Part Number: LH79524N0F100A1;55
• Description: IC, 32BIT MCU, 76.205MHZ, LFBGA-208
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH79524N0F100A1;55

• Controller Family/series: (ARM7)
• No. Of I/o's: 108
• Ram Memory Size: 16KB
• Cpu Speed: 76.205MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 3
• Digital Ic Case Style: LFBGA
• Core Size: 32 Bit
• Core Processor: ARM7
• Speed: 76.2MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LFBGA
• Processor Series: LH795
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: SDK-LH79524-10-3216R - KIT DEVELOPMENT ZOOM SDK LH79524460-3474 - KIT DEV ZOOM STARTER FOR LH79524568-4305 - BOARD EVAL FOR LH79524
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4332; 935285053557; LH79524N0F100A1

System-on-Chip
Preliminary data sheet
nWE
SDCKE
DQM[3:0]
nSDCS[1:0]
SDCLK
SSPFRM
SSPTX
SSPRX
ETHERTXER
ETHERTX[3:0] Output 50 pF
ETHERTXEN
ETHERRXDV
ETHERRX[3:0]
SIGNAL
Output 30 pF
Output 30 pF
Output 30 pF
Output 30 pF
Output 30 pF
Output 50 pF tOVSSPFRM
Output 50 pF
Output 50 pF
Output 50 pF
TYPE LOAD
Input
Input
Input
tOVSSPTX
tOVTXER
tOHTXER
tOVTXEN
tOHTXEN
SYMBOL
tOHSDW
tOVSDW
tISRXDV
tIHRXDV
tISSPRX
tOVTXD
tOHTXD
Table 14. AC Signal Characteristics (Cont’d)
tSDCLK
tISRXD
tIHRXD
tOVDQ
tOHDQ
tOHSC
tOHC0
tOVSC
tOVC0
ETHERNET MAC CONTROLLER (EMC)
SYNCHRONOUS SERIAL PORT (SSP)
NXP Semiconductors
Rev. 01 — 16 July 2007
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
ETHERTXCLK/2 +
ETHERTXCLK/2 +
ETHERTXCLK/2 +
19.37 ns
2.0 ns
2.0 ns
2.0 ns
20 ns
10 ns
10 ns
10 ns
10 ns
MIN.
tSDCLK/2 + 4.5 ns
tSDCLK/2 + 4.5 ns
tSDCLK/2 + 5.0 ns
tSDCLK/2 + 4.5 ns
MAX.
14 ns
14 ns
25 ns
25 ns
25 ns
SDWE Write Enable Valid
SDWE Write Enable Hold
SDCKE Clock Enable Valid
SDCKE Clock Enable Hold
DQM Data Mask Valid
DQM Data Mask Hold
SDCS Data Mask Valid
SDCS Data Mask Hold
SDRAM Clock Period
tOVSSPFRM Output Valid,
Referenced to SSPCLK
SSP Transmit Valid
SSP Receive Setup
Transmit Data Valid after
ETHERTXCLK
Transmit Data Hold after
ETHERTXCLK
Transmit Data Valid after
ETHERTXCLK
Transmit Data Hold after
ETHERTXCLK
Transmit Data Valid after
ETHERTXCLK
Transmit Data Hold after
ETHERTXCLK
Receive Data Setup prior to
ETHERRXCLK
Receive Data Hold prior to
ETHERRXCLK
Receive Data Setup prior to
ETHERRXCLK
Receive Data Hold prior to
ETHERRXCLK
DESCRIPTION
LH79524/LH79525
31