PIC18LF8680-I/PT Microchip Technology, PIC18LF8680-I/PT Datasheet - Page 362

• Manufacturer Part Number: PIC18LF8680-I/PT
• Description: IC, 8BIT MCU, PIC18LF, 40MHZ, PLCC-64
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8680-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 39
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3328Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Core Size: 8 Bit
• Program Memory Size: 32768 Words
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Rohs Compliant: Yes
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3328 B
• Interface Type: I2C, SPI, AUSART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
24.4.1
The user memory may be read to or written from any
location using the table read and table write instruc-
tions. The device ID may be read with table reads. The
Configuration registers may be read and written with
the table read and table write instructions.
In User mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that exe-
cutes from within that block is allowed to read. A table
read instruction that executes from a location outside of
FIGURE 24-4:
DS30491C-page 360
TBLPTR = 000FFFh
Register Values
Results: All table writes disabled to Block n whenever WRTn = 0.
PC = 003FFEh
PC = 008FFEh
PROGRAM MEMORY
CODE PROTECTION
TABLE WRITE (WRTn) DISALLOWED
Program Memory
TBLWT *
TBLWT *
that block is not allowed to read and will result in read-
ing ‘0’s. Figures 24-4 through 24-6 illustrate table write
and table read protection.
Note:
000000h
0007FFh
00BFFFh
00C000h
00FFFFh
000800h
003FFFh
004000h
007FFFh
008000h
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
 2004 Microchip Technology Inc.