FM31274-G Ramtron, FM31274-G Datasheet
FM31274-G
Specifications of FM31274-G
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FM31274-G Summary of contents
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... This is a product in pre-production phase of development. Device characterization is complete and Ramtron does not expect to change the specifications. Ramtron will issue a Product Change Notice if any specification changes are made. Rev. 2.0 Jan. 2011 Processor Companion • ...
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Pin Configuration CNT1 CNT2 CAL/PFO RST 7 8 VSS Ordering Information Base Configuration Memory Size FM31L278 256Kb 256Kb FM31L276 64Kb 64Kb FM31L274 16Kb 16Kb FM31L272 4Kb ...
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A1, A0 Interface SCL SDA LockOut RST PFI + - CAL/PFO - 2.5V + VDD VBAK Pin Descriptions Pin Name Type Pin Description A0, A1 Input Device select inputs are used to address multiple memories on a serial bus. ...
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Overview The FM31L27x family combines a serial nonvolatile RAM with a real-time clock (RTC) and a processor companion. The companion is a highly integrated peripheral including a processor supervisor, a comparator used for early power-fail warning, nonvolatile event counters, and ...
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V VTP TP 2.6V 0 2.9V 1 The watchdog timer can also be used to assert the reset signal (/RST). The watchdog is a free running programmable timer. The period can be software programmed from 100 seconds ...
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The voltage on the PFI input pin is compared to an onboard 1.2V reference. When the PFI input voltage drops below this threshold, the comparator will drive the CAL/PFO pin to a low state. The comparator has 100 mV (max) ...
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W is used for writing new time values. Users should be certain not to load invalid values, such as FFh, to the timekeeping registers. Updates to the timekeeping core occur continuously except when ...
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Years Months CF 8 bits 5 bits Figure 9. Real-Time Clock Core Block Diagram Calibration When the CAL bit in a register 00h is set to 1, the clock enters calibration mode. In calibration mode, the CAL/PFO output ...
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VDD SCL SDA X2 X1 PFI VBAK Layout for Surface Mount Crystal (red = top layer, green = bottom layer) Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion VDD SCL SDA X2 X1 PFI VBAK Layout for Through Hole ...
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Calibration Adjustments Positive Calibration for slow clocks: Calibration will achieve ± 2.17 PPM after calibration Measured Frequency Range Min Max 0 512.0000 511.9989 1 511.9989 511.9967 2 511.9967 511.9944 3 511.9944 511.9922 4 511.9922 511.9900 5 511.9900 511.9878 6 511.9878 ...
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Register Map The RTC and processor companion functions are accessed via 25 special function registers mapped to a separate 2- wire device ID. The interface protocol is described below. The registers contain timekeeping data, control bits, or information flags. A ...
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Register Description Address Description 18h Serial Number Byte SN.63 SN.62 Upper byte of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 17h Serial Number Byte SN.55 SN.54 Byte 6 of the serial ...
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Event Counter Control Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the values without missing count events. The RC bit will be ...
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Watchdog Restart & Flags D7 D6 WTR POR WTR Watchdog Timer Reset Flag: When a watchdog timer fault occurs, the WTR bit will be set must be cleared by the user. Note that both WTR and ...
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CAL/Control D7 D6 OSCEN Reserved /OSCEN /Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the oscillator can save battery power during storage power-up without battery, this bit ...
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Two-wire Interface The FM31L27x employs an industry standard two- wire bus that is familiar to many users. This product is unique since it incorporates two logical devices in one chip. Each logical device can be accessed individually. Although monolithic, it ...
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Slave Address The first byte that the FM31L27x expects after a Start condition is the slave address. As shown in figures below, the slave address contains the Slave ID, Device Select address, and a bit that specifies if the transaction ...
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Start th or Stop condition prior to the 8 data bit. The figures Start By Master S Slave Address 0 By FM31L27x Start ...
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To perform a selective read, the bus master sends out the slave address with the LSB set to 0. This specifies a write operation. ...
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Start By Master S Slave Address 0 A Address MSB By FM31L27x Figure 18. Selective (Random) Memory Read Start By Master S Slave Address By FM31L27x Although not required recommended that A5-A7 in the Register Address byte are ...
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Electrical Specifications Absolute Maximum Ratings Symbol Description V Power Supply Voltage with respect Voltage on any signal pin with respect Backup Supply Voltage BAK T Storage Temperature STG T Lead Temperature (Soldering, ...
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DC Operating Conditions, continued Symbol Parameter V Output Low Voltage ( Output High Voltage ( Pull-up Resistance for /RST Inactive RST R Input Resistance (pulldown) IN A1-A0 for max IN IL ...
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Supervisor Timing (T = -40° 85° Symbol Parameter t /RST Active (low) after V RPU t V < V noise immunity RNR Rise Time Fall Time ...
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AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. ...
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... XXXXXX= part number, P= package type (G=”Green”/RoHS) R=rev, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week FM31L278-G D70023G RIC 1106 Recommended PCB Footprint . . . 7.70 3. 0.65 1.27 0.25 0.50 0.19 ° ...
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Revision History Revision Date 2.0 1/31/2011 Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion Summary Pre-Production. Rev D. Changed I Backup Power section (p.7). and V specs. Added curves to BAK BAK Page ...