SST25LF020A-33-4I-SAE SILICON STORAGE TECHNOLOGY, SST25LF020A-33-4I-SAE Datasheet - Page 16

• Manufacturer Part Number: SST25LF020A-33-4I-SAE
• Description: 2M FLASH MEMORY, SPI EEPROM, SOIC8
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25LF020A-33-4I-SAE

• Memory Size: 2Mbit
• Clock Frequency: 33MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Svhc: No SVHC (18-Jun-2010)
• Device: RoHS Compliant
• Package / Case: SOIC
• Memory Type: Flash
• Memory Configuration: 256K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes

Data Sheet
Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction
with the Enable-Write-Status-Register (EWSR) instruction
to write new values to the BP1, BP0, and BPL bits of the
status register. The Write-Status-Register instruction must
be executed immediately after the execution of the Enable-
Write-Status-Register instruction (very next instruction bus
cycle). This two-step instruction sequence of the EWSR
instruction followed by the WRSR instruction works like
SDP (software data protection) command structure which
prevents any accidental alteration of the status register val-
ues. The Write-Status-Register instruction will be ignored
when WP# is low and BPL bit is set to “1”. When the WP#
is low, the BPL bit can only be set from “0” to “1” to lock-
down the status register, but cannot be reset from “1” to “0”.
©2006 Silicon Storage Technology, Inc.
FIGURE 14: E
SCK
CE#
SO
SI
MODE 3
MODE 0
NABLE
-W
0 1 2 3 4 5 6 7
MSB
RITE
-S
TATUS
50
-R
EGISTER
(EWSR)
HIGH IMPEDANCE
MODE 3
MODE 0
16
MSB
AND
When WP# is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, and BP1 bits in the status reg-
ister can all be changed. As long as BPL bit is set to 0 or
WP# pin is driven high (V
tion of the CE# pin at the end of the WRSR instruction, the
BP0, BP1, and BPL bit in the status register can all be
altered by the WRSR instruction. In this case, a single
WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0 and BP1 bit
at the same time. See Table 3 for a summary description of
WP# and BPL functions. CE# must be driven low before
the command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is
executed. See Figure 14 for EWSR and WRSR instruction
sequences.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
W
RITE
01
-S
2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
TATUS
MSB
7 6 5 4 3 2 1 0
-R
REGISTER IN
EGISTER
STATUS
IH
) prior to the low-to-high transi-
(WRSR) S
S71242-05-000
1242 F14.0
EQUENCE
1/06