SST25LF020A-33-4I-SAE SILICON STORAGE TECHNOLOGY, SST25LF020A-33-4I-SAE Datasheet - Page 15

• Manufacturer Part Number: SST25LF020A-33-4I-SAE
• Description: 2M FLASH MEMORY, SPI EEPROM, SOIC8
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25LF020A-33-4I-SAE

• Memory Size: 2Mbit
• Clock Frequency: 33MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Svhc: No SVHC (18-Jun-2010)
• Device: RoHS Compliant
• Package / Case: SOIC
• Memory Type: Flash
• Memory Configuration: 256K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes

2 Mbit / 4 Mbit SPI Serial Flash
SST25LF020A / SST25LF040A
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE# must be driven high
before the WREN instruction is executed.
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. CE# must be driven high before
the WRDI instruction is executed.
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Enable-Write-
Status-Register instruction does not have any effect and
will be wasted, if it is not followed immediately by the Write-
©2006 Silicon Storage Technology, Inc.
FIGURE 12: W
FIGURE 13: W
RITE
RITE
E
D
NABLE
ISABLE
(WREN) S
(WRDI) S
SCK
CE#
SCK
CE#
SO
SO
SI
EQUENCE
SI
EQUENCE
MODE 3
MODE 0
MODE 3
MODE 0
HIGH IMPEDANCE
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
MSB
0 1 2 3 4 5 6 7
15
Status-Register (WRSR) instruction. CE# must be driven
low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
04
06
1242 F13.0
1242 F12.0
S71242-05-000
Data Sheet
1/06