DSPIC30F4012-20I/SO Microchip Technology, DSPIC30F4012-20I/SO Datasheet - Page 61

• Manufacturer Part Number: DSPIC30F4012-20I/SO
• Description: IC, DSC, 16BIT, 48KB 20MHZ, 5.5V, SOIC28
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F4012-20I/SO

• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 20
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401220ISO

8.0
All of the device pins (except V
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
8.1
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the Parallel Port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the Data Direction register bit is a ‘1’,
then the pin is an input. All port pins are defined as
inputs after a Reset. Reads from the latch (LATx), read
FIGURE 8-1:
© 2010 Microchip Technology Inc.
Note:
I/O PORTS
Parallel I/O (PIO) Ports
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE
Data Bus
WR TRIS
WR LAT +
WR PORT
Read LAT
Read PORT
DD
, V
SS
Read TRIS
Dedicated Port Module
, MCLR and
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
the latch. Writes to the latch, write the latch (LATx).
Reads from the port (PORTx), read the port pins and
writes to the port pins, write the latch (LATx).
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
The format of the registers for PORTx are shown in
Table
The TRISx (Data Direction) register controls the direc-
tion of the pins. The LATx register supplies data to the
outputs and is readable/writable. Reading the PORTx
register yields the state of the input pins, while writing
to the PORTx register modifies the contents of the
LATx register.
A parallel I/O (PIO) port that shares a pin with a periph-
eral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell.
with other peripherals and the associated I/O cell (pad)
to which they are connected.
show the formats of the registers for the shared ports,
PORTB through PORTG.
dsPIC30F4011/4012
8-1.
Figure 8-2
I/O Cell
I/O Pad
shows how ports are shared
Table 8-1
DS70135G-page 61
and
Table 8-2