DSPIC30F4012-20I/SO Microchip Technology, DSPIC30F4012-20I/SO Datasheet - Page 144

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DSPIC30F4012-20I/SO

Manufacturer Part Number
DSPIC30F4012-20I/SO
Description
IC, DSC, 16BIT, 48KB 20MHZ, 5.5V, SOIC28
Manufacturer
Microchip Technology
Series
DsPIC30Fr

Specifications of DSPIC30F4012-20I/SO

Core Frequency
20MHz
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
48KB
Supply Voltage Range
2.5V To 5.5V
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
20
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
6-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F401220ISO

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4012-20I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F4011/4012
The configuration guidelines give the required setup
values for the conversion speeds above 500 ksps,
since they require external V
are some differences in the configuration procedure.
Configuration details that are not critical to the
conversion speed have been omitted.
Figure 20-2
conversion rates above 500 ksps.
FIGURE 20-2:
20.7.1
The configuration for 1 Msps operation is dependent on
whether a single input pin is to be sampled or whether
multiple pins are to be sampled.
20.7.1.1
For conversions at 1 Msps for a single analog input, at
least two sample and hold channels must be enabled.
The analog input multiplexer must be configured so
that the same input pin is connected to both sample
and hold channels. The A/D converts the value held on
one S&H channel while the second S&H channel
acquires a new input sample.
DS70135G-page 144
R2
10
V
1 Msps CONFIGURATION
GUIDELINE
illustrates the recommended circuit for the
DD
Single Analog Input
C2
0.1 μF
A/D CONVERTER VOLTAGE REFERENCE SCHEMATIC
V
DD
C1
0.01 μF
REF
pins usage and there
1
V
V
11
SS
DD
dsPIC30F4011
V
DD
V
DD
R1
10
V
V
33
DD
23
SS
20.7.1.2
The ADC can also be used to sample multiple analog
inputs using multiple sample and hold channels. In this
case, the total 1 Msps conversion rate is divided among
the different input signals. For example, four inputs can
be sampled at a rate of 250 ksps for each signal, or two
inputs could be sampled at a rate of 500 ksps for each
signal. Sequential sampling must be used in this
configuration to allow adequate sampling time on each
input.
V
Multiple Analog Inputs
DD
V
V
DD
DD
C8
1 μF
C5
1 μF
© 2010 Microchip Technology Inc.
V
V
DD
DD
C7
0.1 μF
C4
0.1 μF
V
V
DD
DD
C6
0.01 μF
C3
0.01 μF

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