DSPIC30F3014-20I/PT Microchip Technology, DSPIC30F3014-20I/PT Datasheet - Page 128
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DSPIC30F3014-20I/PT
Manufacturer Part Number
DSPIC30F3014-20I/PT
Description
IC, DSC, 16BIT, 24KB 40MHZ, 5.5V, TQFP44
Manufacturer
Microchip Technology
Series
DsPIC30Fr
Datasheets
1.DSPIC30F3014-30IPT.pdf
(228 pages)
2.DSPIC30F3014-30IPT.pdf
(16 pages)
3.DSPIC30F3014-30IPT.pdf
(6 pages)
4.DSPIC30F3014-30IPT.pdf
(14 pages)
5.DSPIC30F3014-30IPT.pdf
(20 pages)
6.DSPIC30F3014-20IP.pdf
(226 pages)
Specifications of DSPIC30F3014-20I/PT
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
30
Interface Type
I2C/SPI/UART
On-chip Adc
13-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301420IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F3014-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F3014-20I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F3014/4013
18.3.18
The SLOT<3:0> status bits in the DCISTAT SFR indi-
cate the current active time slot. These bits correspond
to the value of the Frame Sync generator counter. The
user may poll these status bits in software when a DCI
interrupt occurs to determine what time slot data was
last received and which time slot data should be loaded
into the TXBUF registers.
18.3.19
The CSDOM control bit controls the behavior of the
CSDO pin during unused transmit slots. A given trans-
mit time slot is unused if it’s corresponding TSEx bit in
the TSCON SFR is cleared.
If the CSDOM bit is cleared (default), the CSDO pin is
low during unused time slot periods. This mode is used
when there are only two devices attached to the serial
bus.
If the CSDOM bit is set, the CSDO pin is tri-stated dur-
ing unused time slot periods. This mode allows multiple
devices to share the same CSDO line in a multichannel
application. Each device on the CSDO line is config-
ured so that it only transmits data during specific time
slots. No two devices transmit data during the same
time slot.
18.3.20
Digital Loopback mode is enabled by setting the
DLOOP control bit in the DCICON1 SFR. When the
DLOOP bit is set, the module internally connects the
CSDO signal to CSDI. The actual data input on the
CSDI I/O pin is ignored in Digital Loopback mode.
18.3.21
When an underflow occurs, one of two actions may
occur depending on the state of the Underflow mode
(UNFM) control bit in the DCICON1 SFR. If the UNFM
bit is cleared (default), the module transmits ‘0’s on the
CSDO pin during the active time slot for the buffer loca-
tion. In this operating mode, the Codec device attached
to the DCI module is simply fed digital ‘silence’. If the
UNFM control bit is set, the module transmits the last
data written to the buffer location. This operating mode
permits the user to send continuous data to the Codec
device without consuming CPU overhead.
DS70138G-page 128
SLOT STATUS BITS
CSDO MODE BIT
DIGITAL LOOPBACK MODE
UNDERFLOW MODE CONTROL BIT
18.4
The frequency of DCI module interrupts is dependent
on the BLEN<1:0> control bits in the DCICON2 SFR.
An interrupt to the CPU is generated each time the set
buffer length has been reached and a shadow register
transfer takes place. A shadow register transfer is
defined as the time when the previously written TXBUF
values are transferred to the transmit shadow registers
and new received values in the receive shadow
registers are transferred into the RXBUF registers.
18.5
18.5.1
The DCI module has the ability to operate while in
Sleep mode and wake the CPU when the CSCK signal
is supplied by an external device (CSCKD = 1). The
DCI module generates an asynchronous interrupt
when a DCI buffer transfer has completed and the CPU
is in Sleep mode.
18.5.2
If the DCISIDL control bit is cleared (default), the mod-
ule continues to operate normally even in Idle mode. If
the DCISIDL bit is set, the module halts when Idle
mode is asserted.
18.6
The AC-Link protocol is a 256-bit frame with one 16-bit
data slot, followed by twelve 20-bit data slots. The DCI
module has two operating modes for the AC-Link pro-
tocol. These operating modes are selected by the
COFSM<1:0> control bits in the DCICON1 SFR. The
first AC-Link mode is called ‘16-bit AC-Link mode’ and
is selected by setting COFSM<1:0> = 10. The second
AC-Link mode is called ‘20-bit AC-Link mode’ and is
selected by setting COFSM<1:0> = 11.
18.6.1
In the 16-bit AC-Link mode, data word lengths are
restricted to 16 bits. Note that this restriction only
affects the 20-bit data time slots of the AC-Link proto-
col. For received time slots, the incoming data is simply
truncated to 16 bits. For outgoing time slots, the 4 LSbs
of the data word are set to ‘0’ by the module. This trun-
cation of the time slots limits the A/D and DAC data to
16 bits but permits proper data alignment in the TXBUF
and RXBUF registers. Each RXBUF and TXBUF
register contains one data time slot value.
DCI Module Interrupts
DCI Module Operation During CPU
Sleep and Idle Modes
AC-Link Mode Operation
DCI MODULE OPERATION DURING
CPU SLEEP MODE
DCI MODULE OPERATION DURING
CPU IDLE MODE
16-BIT AC-LINK MODE
2010 Microchip Technology Inc.