DSPIC30F3014-20I/PT Microchip Technology, DSPIC30F3014-20I/PT Datasheet - Page 124
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DSPIC30F3014-20I/PT
Manufacturer Part Number
DSPIC30F3014-20I/PT
Description
IC, DSC, 16BIT, 24KB 40MHZ, 5.5V, TQFP44
Manufacturer
Microchip Technology
Series
DsPIC30Fr
Datasheets
1.DSPIC30F3014-30IPT.pdf
(228 pages)
2.DSPIC30F3014-30IPT.pdf
(16 pages)
3.DSPIC30F3014-30IPT.pdf
(6 pages)
4.DSPIC30F3014-30IPT.pdf
(14 pages)
5.DSPIC30F3014-30IPT.pdf
(20 pages)
6.DSPIC30F3014-20IP.pdf
(226 pages)
Specifications of DSPIC30F3014-20I/PT
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Package
44TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
30
Interface Type
I2C/SPI/UART
On-chip Adc
13-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301420IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F3014-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F3014-20I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F3014/4013
size and Frame Sync generator control bits. A new I
data transfer boundary is marked by a high-to-low or a
low-to-high transition edge on the COFS pin.
18.3.6
When the DCI module is operating as a Frame Sync
slave (COFSD = 1), data transfers are controlled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
In the Multichannel mode, a new data frame transfer
begins one CSCK cycle after the COFS pin is sampled
high (see
resets the Frame Sync generator logic.
FIGURE 18-2:
FIGURE 18-3:
FIGURE 18-4:
DS70138G-page 124
Note:
Figure
SLAVE FRAME SYNC OPERATION
CSDO or CSDI
CSDI or CSDO
CSDI/CSDO
A 5-bit transfer is shown here for illustration purposes. The I
will be system dependent.
18-2). The pulse on the COFS pin
BIT_CLK
CSCK
COFS
SYNC
CSCK
FRAME SYNC TIMING, MULTICHANNEL MODE
FRAME SYNC TIMING, AC-LINK START-OF-FRAME
I
2
S INTERFACE FRAME SYNC TIMING
WS
MSB
bit 2
S12
MSB
bit 1
S12
2
S12
LSb
S
MSb
Tag
bit 14
In the I
CSCK cycle after a low-to-high or a high-to-low transi-
tion is sampled on the COFS pin. A rising or falling
edge on the COFS pin resets the Frame Sync
generator logic.
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame is transferred one CSCK cycle
after the COFS pin is sampled high.
The COFSG and WS bits must be configured to
provide the proper frame length when the module is
operating in the Slave mode. Once a valid Frame Sync
pulse has been sampled by the module on the COFS
pin, an entire data frame transfer takes place. The
module will not respond to further Frame Sync pulses
until the data frame transfer has completed.
Tag
LSB MSB
bit 13
Tag
2
2
S protocol does not specify word length – this
S mode, a new data word is transferred one
LSB
2010 Microchip Technology Inc.
LSB