DSPIC30F2020-20E/SO Microchip Technology, DSPIC30F2020-20E/SO Datasheet - Page 29

• Manufacturer Part Number: DSPIC30F2020-20E/SO
• Description: IC, DSC, 16BIT, 12KB 40MHZ, 5.5V, SOIC28
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F2020-20E/SO

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.4
Programming
Section 11.4.1 “Programming Operations”
Section 11.4.3
Programming
Step-by-step procedures are described in
“Bulk
Section 11.11 “Reading the Application ID
All programming operations must use serial execution,
as described in
11.4.1
Flash memory write and erase operations are
controlled by the NVMCON register. Programming is
performed by setting NVMCON to select the type of
erase operation
(Table
programming and initiating the programming by setting
the WR control bit, NVMCON<15>.
In ICSP mode, all programming operations are
externally timed. An external 2 msec delay must be
used between setting the WR control bit and clearing
the WR control bit to complete the programming
operation.
TABLE 11-2:
TABLE 11-3:
© 2010 Microchip Technology Inc.
0x407F
0x406E
0x404E
0x4042
0x4072
0x4071
0x4008
0x4001
NVMCON
NVMCON
Value
Value
11-3), writing a key sequence to enable the
Flash Memory Programming in
ICSP Mode
Erasing
PROGRAMMING OPERATIONS
Writes 1 word to configuration
memory.
Writes 1 row (32 instruction words) into
1 panel of program memory.
Erases all code memory, data memory,
executive memory and code-protect
bits (does not erase UNIT ID).
Erases Boot Segment, General Seg-
ment and Interrupt Vector Table, then
erase FBS and FGS Configuration
registers.
Erases General Segment, then erase
FGS Configuration register.
Erases General Segment without eras-
ing Interrupt Vector Table (when Boot
Segment is not defined).
Erases all executive memory.
Erases 1 row (32 instruction words)
from 1 panel of code memory.
Cycle”.
Section 11.2 “ICSP
in
NVMCON ERASE
OPERATIONS
NVMCON WRITE
OPERATIONS
“Starting
(Table
ICSP
Program
Erase Operation
Write Operation
11-2) or write operation
mode
and
Memory”
is
Operation”.
Stopping
described
Section 11.5
Word”.
through
through
in
a
11.4.2
Writes to the WR bit (NVMCON<15>) are locked to
prevent accidental programming from taking place.
Writing a key sequence to the NVMKEY register
unlocks the WR bit and allows it to be written to. The
unlock sequence is performed as follows:
11.4.3
Once the unlock key sequence has been written to the
NVMKEY register, the WR bit (NVMCON<15>) is used
to start and stop an erase or write cycle. Setting the WR
bit initiates the programming cycle. Clearing the WR bit
terminates the programming cycle.
All erase and write cycles must be externally timed. An
external delay must be used between setting and
clearing the WR bit. Starting and stopping a
programming cycle is performed as follows:
11.5
The procedure for bulk erasing program memory (all
code memory, data memory, executive memory and
code-protect bits) consists of setting NVMCON to
0x407F, unlocking NVMCON for erasing and then
executing the programming cycle.
Table 11-4
bulk erasing program memory. This process includes
the ICSP command code, which must be transmitted
(for each instruction) to the Least Significant bit first
using the PGC and PGD pins (see
Note:
Note:
MOV
MOV
MOV
MOV
BSET
<Wait 2 msec>
BCLR
Bulk Erasing Program Memory
shows the ICSP programming process for
UNLOCKING NVMCON FOR
PROGRAMMING
Any working register or working register
pair can be used to write the unlock
sequence.
STARTING AND STOPPING A
PROGRAMMING CYCLE
Program memory must be erased before
writing any data to program memory.
#0x55, W8
W8, NVMKEY
#0xAA, W9
W9, NVMKEY
NVMCON, #WR
NVMCON, #WR
Figure
DS70284C-page 29
11-2).