DSPIC30F2020-20E/SO Microchip Technology, DSPIC30F2020-20E/SO Datasheet - Page 14

• Manufacturer Part Number: DSPIC30F2020-20E/SO
• Description: IC, DSC, 16BIT, 12KB 40MHZ, 5.5V, SOIC28
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F2020-20E/SO

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

6.5
To allow portability of code, the programmer must read
the Configuration register locations from the hex file
(see
information is not present in the hex file, a simple
warning
programmer. Similarly, while saving a hex file, all
configuration information must be included. An option
can be provided not to include the configuration
information.
Microchip Technology Inc. feels strongly that this
feature is important for the benefit of the end customer.
6.6
Checksums for the dsPIC30F SMPS are 16 bits in size.
The checksum is calculated by summing the following:
• Contents of code memory locations
• Contents of Configuration registers
TABLE 6-2:
DS70284C-page 14
dsPIC30F1010
dsPIC30F2020
dsPIC30F2023
Item Description:
SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked) = Byte sum of ((FBS&0x000F)+(FGS&0x0007)+(FOSCSEL&0x0003)+
(FOSC&0x00E7)+(FWDT&0x00DF)+(FPOR(0x0007))+(FICD(0x0083))
SMPS Device
Appendix A: “Hex File
Configuration Information in the
Hex File
Checksum Computation
message
CHECKSUM COMPUTATION
should
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Read Code
Protection
Format”). If configuration
be
issued
CFGB + SUM(0:000FFF)
CFGB
CFGB + SUM(0:001FFF)
CFGB
CFGB + SUM(0:001FFF)
CFGB
Checksum Computation
by
the
All memory locations are summed one byte at a time,
using only their native data size. More specifically,
configuration and device ID registers are summed by
adding the lower two bytes of these locations (the
upper byte is ignored), while code memory is summed
by adding all three bytes of code memory.
Table 6-2
made for each dsPIC30F SMPS device. Computations
for read code protection are shown both enabled and
disabled. The checksum values assume that the
Configuration registers are also erased. However,
when code protection is enabled, the value of the FGS
register is assumed to be 0x0.
Note:
shows how this 16-bit computation can be
The
depending on the code-protect setting.
Table 6-2
checksum for an unprotected device and
a read-protected device. Regardless of
the code-protect setting, the Configuration
registers can always be read.
0xEA69
0xD269
0xD269
Erased
0x251
0x251
0x251
Value
checksum
describes how to compute the
© 2010 Microchip Technology Inc.
0xAAAAAA at 0x0
Code Address
calculation
Value with
and Last
0xD06B
0xD06B
0xE86B
0x251
0x251
0x251
differs