SC16C752BIB48 NXP Semiconductors, SC16C752BIB48 Datasheet - Page 9

• Manufacturer Part Number: SC16C752BIB48
• Description: IC, UART, DUAL, 64BYTE FIFO, 16C752
• Manufacturer: NXP Semiconductors

Specifications of SC16C752BIB48

• No. Of Channels: 2
• Data Rate: 5Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Uart Features: DMA Signalling Capability, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
SC16C752B
Product data sheet
Fig 6.
When CTSn is LOW, the transmitter keeps sending serial data out.
When CTSn goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current
byte, but is does not send the next byte.
When CTSn goes from HIGH to LOW, the transmitter begins sending data again.
CTS functional timing
CTSn
6.2.2 Auto-CTS
TXn
6.3 Software flow control
The transmitter circuitry checks CTSn before sending the next data byte. When CTSn is
active, the transmitter sends the next byte. To stop the transmitter from sending the
following byte, CTSn must be de-asserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system. When
flow control is enabled, CTSn level changes do not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends
any data present in the transmit FIFO and a receiver overrun error may result.
Software flow control is enabled through the enhanced feature register and the modem
control register. Different combinations of software flow control can be enabled by setting
different combinations of EFR[3:0].
Table 3.
EFR[3]
0
1
0
1
X
X
X
1
0
1
EFR[2]
0
0
1
1
X
X
X
0
1
1
Start
Software flow control options (EFR[0:3])
All information provided in this document is subject to legal disclaimers.
byte 0 to 7
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
EFR[1]
X
X
X
X
0
1
0
1
1
1
Rev. 6 — 30 November 2010
Stop
EFR[0]
X
X
X
X
0
0
1
1
1
1
Table 3
TX, RX software flow controls
no transmit flow control
transmit Xon1, Xoff1
transmit Xon2, Xoff2
transmit Xon1, Xon2, Xoff1, Xoff2
no receive flow control
receiver compared Xon1, Xoff1
receiver compares Xon2, Xoff2
transmit Xon1, Xoff1
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
transmit Xon2, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
transmit Xon1, Xon2, Xoff1, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
shows software flow control options.
Start
byte 0 to 7
SC16C752B
002aaa227
Stop
© NXP B.V. 2010. All rights reserved.
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