78Q8430-100CGT/F TERIDIAN, 78Q8430-100CGT/F Datasheet - Page 7

• Manufacturer Part Number: 78Q8430-100CGT/F
• Description: IC, ETHERNET TXRX, IEEE 802.3, LQFP-100
• Manufacturer: TERIDIAN

Specifications of 78Q8430-100CGT/F

• No. Of Ports: 2
• Ethernet Type: IEEE 802.3x, IEEE 802.3u, IEEE 802.3-2000
• Ic Interface Type: Host Bus, JTAG
• Supply Voltage Range: 0V To 3.3V
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SIGNAL
TX_CLK
TX_EN
TXD[3:0]
TX_ER
CRS
COL
RX_CLK
PIN DESCRIPTION
LEGEND
MII (MEDIA INDEPENDENT INTERFACE)
Page: 7 of 39
TYPE
CIU
CIS
CO
A
S
DESCRIPTION
Analog Pin
TTL-level Input w/ Pull-up
TTL-level Input w/ Schmitt Trigger
CMOS Output
Supply
PIN
15
16
[20:17] CI
14
22
21
12
TYPE DESCRIPTION
COZ
CI
CI
COZ
COZ
COZ
TRANSMIT CLOCK: TX_CLK is a continuous clock, which provides a timing
reference for the TX_EN, TX_ER and TXD[3:0] signals from the MAC. The clock
frequency is 25MHz in 100BASE-TX mode and 2.5MHz in 10BASE-T mode. This
pin is tri-stated in isolate mode and the TXHIM mode.
TRANSMIT ENABLE: TX_EN is asserted by the MAC to indicate that valid data for
transmission is present on the TXD[3:0] pins.
TRANSMIT DATA: TXD[3:0] receives data from the MAC for transmission on a
nibble basis. This data is captured on the rising edge of TX_CLK when TX_EN is
high.
TRANSMIT ERROR: TX_ER is asserted high by the MAC to request that an error
code-group be transmitted when TX_EN is high. In PCS bypass mode, this pin
becomes the MSB of the transmit 5-bit code group.
CARRIER SENSE: When the 78Q2123/78Q2133 are not in repeater mode, CRS is
high whenever a non-idle condition exists on either the transmitter or the receiver.
In repeater mode, CRS is only active when a non-idle condition exists on the
receiver. This pin is tri-stated in isolate mode.
COLLISION: COL is asserted high when a collision has been detected on the
media. In 10BASE-T mode COL is also used for the SQE test function. This pin is
tri-stated in isolate mode. During half duplex operation, the rising edge of COL will
occasionally occur upon the rising edge of TX_CLK.
RECEIVE CLOCK: RX_CLK is a continuous clock, which provides a timing
reference to the MAC for the RX_DV, RX_ER and RXD[3:0] signals. The clock
frequency is 25MHz in 100BASE-TX mode and 2.5MHz in 10BASE-T mode. To
reduce power consumption in 100BASE-TX mode, the 78Q2123/78Q2133 provide
an optional mode, enabled through MR16.0, in which RX_CLK is held inactive (low)
when no receive data is detected. This pin is tri-stated in isolate mode.
©
2006 Teridian Semiconductor Corporation
TYPE
COZ
CIO
CI
G
DESCRIPTION
TTL-level Input
TTL-compatible Bi-directional Pin
Tristate-able CMOS output
Ground
10/100BASE-TX Transceiver
Rev 1.1