ADXL312WACPZ-RL Analog Devices Inc, ADXL312WACPZ-RL Datasheet - Page 27

ADXL312WACPZ-RL

Manufacturer Part Number

ADXL312WACPZ-RL

Description

IC ACCEL SPI/I2C 3AX 32LFCSP

Manufacturer

Analog Devices Inc

Datasheet

1.ADXL312ACPZ-RL.pdf (32 pages)

Specifications of ADXL312WACPZ-RL

Axis

X, Y, Z

Acceleration Range

±1.5g, 3g, 6g, 12g

Sensitivity

345LSB/g, 172LSB/g, 86LSB/g, 43LSB/g

Voltage - Supply

2 V ~ 3.6 V

Output Type

Digital

Bandwidth

6.25 Hz ~ 3200 Hz

Interface

I²C, SPI

Mounting Type

Surface Mount

Package / Case

32-LFQFN, CSP Exposed Pad

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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DATA FORMATTING OF UPPER DATA RATES

Formatting of output data at the 3200 Hz and 1600 Hz output

data rates changes depending on the mode of operation (full-

resolution or fixed 10-bit) and the selected output range.

When in full-resolution or ±1.5 g, 10-bit operation, the LSB of

the output data-word is always 0. When data is right justified,

this corresponds to Bit D0 of the DATAx0 register, as shown in

Figure 32. When data is left justified and the part is operating in

±1.5 g, 10-bit mode, the LSB of the output data-word is Bit D6

of the DATAx0 register. In full-resolution operation when data

is left justified, the location of the LSB changes according to the

selected output range. For a range of ±1.5 g, the LSB is Bit D6 of

Figure 32. Data Formatting of Full-Resolution and ±1.5 g, 10-Bit Modes of Operation When Output Data Is Right Justified

Figure 33. Data Formatting of Full-Resolution and ±1.5 g, 10-Bit Modes of Operation When Output Data Is Left Justified

THE ±3g AND ±6g FULL-RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE ±1.5g

AND ±12g FULL-RESOLUTION MODES, BUT THE MSB LOCATION CHANGES TO BIT D2 AND

BIT D3 OF THE DATAx1 REGISTER FOR ±3g AND ±6g, RESPECTIVELY.

DATAx1 REGISTER

OUTPUT DATA-WORD FOR

±12g, FULL-RESOLUTION MODE.

FOR 3200Hz AND 1600Hz OUTPUT DATA RATES, THE LSB IN THESE MODES IS ALWAYS 0.

ADDITIONALLY, ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT

DATA IS LEFT JUSTIFIED.

DATAx1 REGISTER

MSB FOR ALL MODES

OF OPERATION WHEN

LEFT JUSTIFIED.

LSB FOR ±1.5g, FULL-RESOLUTION

LSB FOR ±12g, FULL-RESOLUTION MODE.

LSB FOR ±3g, FULL-RESOLUTION MODE.

LSB FOR ±6g, FULL-RESOLUTION MODE.

AND ±1.5g, 10-BIT MODES.

Rev. 0 | Page 27 of 32

the DATAx0 register; for ±3 g, Bit D5 of the DATAx0 register;

for ±6 g, Bit D4 of the DATAx0 register; and for ±12 g, Bit D3

of the DATAx0 register. This is shown in Figure 33.

The use of 3200 Hz and 1600 Hz output data rates for fixed 10-bit

operation in the ±3 g, ±6 g, and ±12 g output ranges provides an

LSB that is valid and that changes according to the applied accel-

eration. Therefore, in these modes of operation, Bit D0 is not

always 0 when output data is right justified, and Bit D6 is not

always 0 when output data is left justified. Operation at any data

rate of 800 Hz or lower also provides a valid LSB in all ranges and

modes that changes according to the applied acceleration.

OUTPUT DATA-WORD FOR ±1.5g, 10-BIT

AND ±1.5g, FULL-RESOLUTION MODES.

DATAx0 REGISTER

ADXL312

ADXL312WACPZ-RL Analog Devices Inc, ADXL312WACPZ-RL Datasheet - Page 27

ADXL312WACPZ-RL

Specifications of ADXL312WACPZ-RL

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