ADXL312WACPZ-RL Analog Devices Inc, ADXL312WACPZ-RL Datasheet - Page 17

• Manufacturer Part Number: ADXL312WACPZ-RL
• Description: IC ACCEL SPI/I2C 3AX 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADXL312WACPZ-RL

• Axis: X, Y, Z
• Acceleration Range: ±1.5g, 3g, 6g, 12g
• Sensitivity: 345LSB/g, 172LSB/g, 86LSB/g, 43LSB/g
• Voltage - Supply: 2 V ~ 3.6 V
• Output Type: Digital
• Bandwidth: 6.25 Hz ~ 3200 Hz
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 32-LFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERRUPTS
The ADXL312 provides two output pins for driving interrupts:
INT1 and INT2. Both interrupt pins are push-pull, low impedance
pins with output specifications shown in Table 12. The default
configuration of the interrupt pins is active high. This can be
changed to active low by setting the INT_INVERT bit in the
DATA_FORMAT (Address 0x31) register. All functions can be
used simultaneously, with the only limiting feature being that
some functions may need to share interrupt pins.
Interrupts are enabled by setting the appropriate bit in the
INT_ENABLE register (Address 0x2E) and are mapped to either
the INT1 or INT2 pin based on the contents of the INT_MAP
register (Address 0x2F). When initially configuring the interrupt
pins, it is recommended that the functions and interrupt mapping
be done before enabling the interrupts. When changing the con-
figuration of an interrupt, it is recommended that the interrupt be
disabled first, by clearing the bit corresponding to that function in
the INT_ENABLE register, and then the function be reconfigured
before enabling the interrupt again. Configuration of the functions
while the interrupts are disabled helps to prevent the accidental
generation of an interrupt before desired.
The interrupt functions are latched and cleared by either reading
the data registers (Address 0x32 to Address 0x37) until the inter-
rupt condition is no longer valid for the data-related interrupts
or by reading the INT_SOURCE register (Address 0x30) for the
remaining interrupts. This section describes the interrupts that
can be set in the INT_ENABLE register and monitored in the
INT_SOURCE register.
Table 12. Interrupt Pin Digital Output
Parameter
Digital Output
Pin Capacitance
Rise/Fall Time
1
2
3
Limits based on characterization results, not production tested.
Rise time is measured as the transition time from V
Fall time is measured as the transition time from V
Low Level Output Voltage (V
High Level Output Voltage (V
Low Level Output Current (I
High Level Output Current (I
Rise Time (t
Fall Time (t
F
R
)
)
3
2
OL
OH
OL
OH
)
)
)
)
OH, min
OL, max
to V
to V
Test Conditions
I
I
V
V
f
C
C
OL, max
OL
OH
IN
OH, min
OL
OH
LOAD
LOAD
= 1 MHz, V
= 300 μA
= −150 μA
= V
= V
of the interrupt pin.
of the interrupt pin.
= 150 pF
= 150 pF
OL, max
OH, min
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IN
= 2.5 V
DATA_READY
The DATA_READY bit is set when new data is available and is
cleared when no new data is available.
Activity
The activity bit is set when acceleration greater than the value stored
in the THRESH_ACT register (Address 0x24) is experienced.
Inactivity
The inactivity bit is set when acceleration of less than the value
stored in the THRESH_INACT register (Address 0x25) is
experienced for more time than is specified in the TIME_INACT
register (Address 0x26). The maximum value for TIME_INACT is
255 sec.
Watermark
The watermark bit is set when the number of samples in FIFO
equals the value stored in the samples bits (Register FIFO_CTL,
Address 0x38). The watermark bit is cleared automatically when
FIFO is read, and the content returns to a value below the value
stored in the samples bits.
Overrun
The overrun bit is set when new data replaces unread data. The
precise operation of the overrun function depends on the FIFO
mode. In bypass mode, the overrun bit is set when new data
replaces unread data in the DATAX, DATAY, and DATAZ registers
(Address 0x32 to Address 0x37). In all other modes, the overrun
bit is set when FIFO is filled. The overrun bit is automatically
cleared when the contents of FIFO are read.
0.8 × V
Min
300
DD I/O
Limit
1
0.2 × V
−150
Max
210
150
8
DD I/O
ADXL312
Unit
V
V
μA
μA
pF
ns
ns