DC1241B-BA Linear Technology, DC1241B-BA Datasheet - Page 22

• Manufacturer Part Number: DC1241B-BA
• Description: BOARD EVAL LTM9001-BA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1241B-BA

• Design Resources: DC1241B Schematic
• Frequency: 0Hz ~ 300MHz
• Features: LTM9001 16bit Receiver Subsystem, DC-300MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9001
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9001
• Lead Free Status / RoHS Status: Not applicable / Not applicable

LTM9001-Ax/LTM9001-Bx
APPLICATIONS INFORMATION
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3V
The lower limit of the sample rate is determined by the
droop of the sample and hold circuits. The pipelined ar-
chitecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specifi ed minimum operating frequency
for the LTM9001 is 1Msps.
22
Figure 9. ENC Drive Using a CMOS to PECL Translator
MC100LVELT22
V
THRESHOLD
Figure 8. Single-Ended ENC Drive,
Not Recommended for Low Jitter
D0
DD
= 1.6V
3.3V
or 2/3V
Q0
Q0
0.1μF
261Ω
165Ω
1.6V
DD
3.3V
using external resistors.
ENC
ENC
165Ω
261Ω
ENC
ENC
+
–
+
–
LTM9001
100Ω
LTM9001
9001F8
9001 F09
DIGITAL OUTPUTS
Digital Output Modes
The LTM9001 can operate in four digital output modes:
standard LVDS, low power LVDS, full rate CMOS, and
demultiplexed CMOS. The LVDS pin selects the mode of
operation. This pin has a four level logic input, centered at
0, 1/3V
can be used to set the 1/3V
Table 4 shows the logic states for the LVDS pin.
Table 4. LVDS Pin Function
Digital Output Buffers (CMOS Modes)
Figure 10 shows an equivalent circuit for a single output
buffer in CMOS mode, full-rate or demultiplexed. Each
buffer is powered by OV
ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to low voltages.
The internal resistor in series with the output makes the
output appear as 50Ω to external circuitry and eliminates
the need for external damping resistors.
LATCH
FROM
DATA
Figure 10. Equivalent Circuit for a Digital Output Buffer
0V(GND)
DD
1/3V
2/3V
PREDRIVER
LVDS
V
, 2/3V
LOGIC
DD
V
DD
DD
DD
DD
and V
DD
DD
V
DD
. An external resistive divider
and OGND, isolated from the
DD
DIGITAL OUTPUT MODE
Demultiplexed CMOS
and 2/3V
Low Power LVDS
Full-Rate CMOS
LVDS
OV
DD
LTM9001
DD
43Ω
9001 F10
logic levels.
OV
OGND
DD
TYPICAL
DATA
OUTPUT
0.5V
TO 3.6V
9001fc