DC1241B-BA Linear Technology, DC1241B-BA Datasheet - Page 15

• Manufacturer Part Number: DC1241B-BA
• Description: BOARD EVAL LTM9001-BA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1241B-BA

• Design Resources: DC1241B Schematic
• Frequency: 0Hz ~ 300MHz
• Features: LTM9001 16bit Receiver Subsystem, DC-300MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9001
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9001
• Lead Free Status / RoHS Status: Not applicable / Not applicable

PIN FUNCTIONS
Digital Outputs
For CMOS Mode, Full Rate or Demultiplexed
DA0 to DA15 (Pins E9 to H5): Digital Outputs, A Bus.
DA15 is the MSB. Output bus for full rate CMOS mode
and demultiplexed mode.
CLKOUTA (Pin E8): Inverted Data Valid Output. CLKOUTA
will toggle at the sample rate in full rate CMOS mode or
at 1/2 the sample rate in demultiplexed mode. Latch the
data on the rising edge of CLKOUTA.
OFB (Pin E6): Overfl ow/Underfl ow Digital Output for the
B Bus. OFB is high when an overfl ow or underfl ow has
occurred on the B bus. OFB is in a high impedance state
in full rate CMOS mode.
DB0 to DB15 (Pins B5 to D9): Digital Outputs, B Bus. DB15
is the MSB. Active in demultiplexed mode. The B bus is in
a high impedance state in full rate CMOS mode.
Pin Confi guration (LVDS Outputs/CMOS Outputs)
H
G
D
E
C
B
A
J
F
ENC
ENC
GND
GND
GND
GND
V
IN
IN
1
CC
–
+
+
–
GND
GND
GND
GND
GND
GND
GND
GND
V
2
CC
AMPSHDN
ADCSHDN
SENSE
MODE
RAND
DITH
PGA
DNC
DNC
3
Top View of LGA Pinout (Looking Through Component)
IN
IN
ENC
V
DNC
ENC
ALL ELSE
= GND
CC
–
+
GND
GND
GND
GND
GND
GND
GND
GND
GND
–
+
4
H
G
D
C
B
A
J
F
E
CONTROL
1
CONTROL
2
3
D14
OF
D0
D0
OF
OGND
LVDS
–
4
TOP VIEW
V
V
V
+
+
+
–
/DA15
DD
5
/DA12
/DB1
/DB0
/OFA
DD
DD
DATA
5
OGND
CLKOUTB (Pin E7): Data Valid Output. CLKOUTB will toggle
at the sample rate in full rate CMOS mode or at 1/2 the
sample rate in demultiplexed mode. Latch the data on the
falling edge of CLKOUTB.
OFA (Pin G5): Overfl ow/Underfl ow Digital Output for the
A Bus. OFA is high when an overfl ow or underfl ow has
occurred on the A bus.
For LVDS Mode, Standard or Low Power
D0
puts. All LVDS outputs require differential 100Ω termination
resistors at the LVDS receiver. D15
CLKOUT
Latch data on the rising edge of CLKOUT
of CLKOUT
OF
OF is high when an over or under fl ow has occurred.
6
OV
–
–
7
DD
/D0
/OF
CLKOUT
D14
D15
D15
D6
8
D9
D4
D1
LTM9001-Ax/LTM9001-Bx
9001 LGA01
+
OV
+
–
–
–
+
–
–
–
9
–
/DB12
to D15
(Pins H5, G5): Overfl ow/Underfl ow Digital Output.
6
/DA11
/DA13
/DA14
/DA1
/DB8
/DB2
/CLKOUT
DD
–
–
/OFB CLKOUT
OGND
OV
OGND
.
DD
–
/D15
+
D13
D12
D13
D6
(Pins E6, E7): LVDS Data Valid Output.
D9
D4
D1
D2
+
+
+
+
+
+
+
–
(Pins B5 to G6): LVDS Digital Out-
/DB13
+
–
7
/DA10
/DA2
/CLKOUTB D8
/DB9
/DB3
/DB4
/DA8
/DA9
D12
D11
D10
D7
D5
+
D3
D2+/DB5
–
/CLKOUTA
/D15
OGND
–
–
+
/DB14
/DB10
–
–
–
8
/DB7
/DA7
/DA5
/DA3
–
is the MSB.
+
, falling edge
D11
D10
D7
D5
D8
D3
OGND
OGND
OV
+
+
15
+
–
/DB15
/DB11
+
+
9
/DA0
/DB6
/DA6
/DA4
DD
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