DC1241B-BA Linear Technology, DC1241B-BA Datasheet - Page 21

• Manufacturer Part Number: DC1241B-BA
• Description: BOARD EVAL LTM9001-BA
• Manufacturer: Linear Technology
• Type: Baseband Receiverr

Specifications of DC1241B-BA

• Design Resources: DC1241B Schematic
• Frequency: 0Hz ~ 300MHz
• Features: LTM9001 16bit Receiver Subsystem, DC-300MHz LPF
• Tool / Board Applications: Wireless Connectivity-ZigBee, RF, Infrared, USB
• Mcu Supported Families: LTM9001
• Development Tool Type: Hardware - Eval/Demo Board
• For Use With/related Products: LTM9001
• Lead Free Status / RoHS Status: Not applicable / Not applicable

APPLICATIONS INFORMATION
PGA Pin
The PGA pin selects between two gain settings for the
ADC front-end. PGA = low selects the maximum input
span; PGA = high selects a 3.5dB lower input span. The
high input range has the best SNR. For applications with
high linearity requirements, the low input range will have
improved distortion; however, the SNR will be 1.8dB worse.
See the Typical Performance Characteristics section.
Driving the Encode Inputs
The noise performance of the converter can depend on
the encode signal quality as much as the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter. In applications where jitter
is critical (high input frequencies), take the following into
consideration:
1. Differential drive should be used.
2. Use the largest amplitude possible. If using transformer
coupling, use a higher turns ratio to increase the am-
plitude.
ENC
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Figure 7a. Equivalent Encode Input Circuit
100Ω
LTM9001
V
DD
V
DD
1.6V
6k
1.6V
6k
V
DD
TO INTERNAL
ADC CLOCK
DRIVERS
9001 F07a
3. If the ADC is clocked with a fi xed frequency sinusoidal
4. Balance the capacitance and series resistance at both
The encode inputs have a common mode range of 1.2V
to V
single-ended drive.
The encode clock inputs have a differential 100Ω input
impedance. For 50Ω inputs e.g. signal generators, an
additional 100Ω impedance will provide an impedance
match, as shown in Figure 7b.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTM9001-Ax is 130Msps
and 160Msps for LTM9001-BA. For the ADC to operate
properly the encode signal should have a 50% (±5%)
duty cycle. Each half cycle must have at least 3.65ns
(LTM9001-Ax, or 2.97ns for LTM9001-BA) for the ADC
internal circuitry to have enough settling time for proper
operation. Achieving a precise 50% duty cycle is easy with
differential sinusoidal drive using a transformer or using
symmetric differential logic such as PECL or LVDS. When
using a single-ended encode signal asymmetric rise and fall
times can result in duty cycles that are far from 50%.
signal, fi lter the encode signal to reduce wideband
noise.
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
DD
LTM9001-Ax/LTM9001-Bx
. Each input may be driven from ground to V
0.1μF
0.1μF
T1 = M/A-COM ETC1-1-13
Figure 7b. Transformer Driven Encode
T1
50Ω
50Ω
0.1μF
8.2pF
100Ω
LTM9001
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for