EVAL-ADF4153EBZ1 Analog Devices Inc, EVAL-ADF4153EBZ1 Datasheet - Page 7

• Manufacturer Part Number: EVAL-ADF4153EBZ1
• Description: BOARD EVAL FOR ADF4153
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4153EBZ1

• Main Purpose: Timing, Frequency Synthesizer
• Embedded: No
• Utilized Ic / Part: ADF4153
• Primary Attributes: Single Fractional-N PLL
• Secondary Attributes: 1.75GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
LFCSP
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
CPGND
AGND
RF
RF
REF
AV
R
Figure 3. TSSOP Pin Configuration
SET
IN
IN
CP
DD
IN
B
A
1
2
3
4
5
6
7
8
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
SDV
CLK
DATA
LE
MUXOUT
DV
V
SET
P
IN
IN
DD
DD
(Not to Scale)
IN
ADF4153
B
A
DD
TOP VIEW
Description
Connecting a resistor between R
The relationship between I
where R
Charge Pump Output. When enabled, CP provides ±I
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This pin should be decoupled to the ground plane
with a small bypass capacitor, typically 100 pF (see Figure 12).
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. AV
voltage as DV
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ (see Figure 11). This input can be driven from a TTL or CMOS crystal oscillator,
or it can be ac-coupled.
Digital Ground.
Σ-Δ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible
to this pin. SDV
Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is
latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is
a high impedance CMOS input.
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one
of four latches; the latch is selected using the control bits.
This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be externally accessed.
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
the same voltage as AV
Charge Pump Power Supply. This should be greater than or equal to V
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
16
15
14
13
12
11
10
9
V
DV
MUXOUT
LE
DATA
CLK
SDV
DGND
P
I
DD
CPMAX
DD
SET
= 5.1 kΩ and I
=
DD
R
.
DD
25
SET
has a value of 3 V ± 10%. SDV
5 .
DD
Rev. D | Page 7 of 24
CPMAX
.
CP
and R
= 5 mA.
SET
SET
and ground sets the maximum charge pump output current.
is
DD
has a value of 3 V ± 10%. AV
DD
must have the same voltage as DV
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE
CPGND
DD
CP
AGND
AGND
RF
RF
THAT MUST BE CONNECTED TO GND.
has a value of 3 V ± 10%. DV
to the external loop filter, which in turn
IN
IN
Figure 4. LFCSP Pin Configuration
B
A
1
2
3
4
5
(Not to Scale)
ADF4153
TOP VIEW
PIN 1
INDICATOR
DD
/2 and an equivalent input
DD
. In systems where V
DD
must have the same
15 MUXOUT
14 LE
13 DATA
12 CLK
11 SDV
DD
DD
DD
must have
.
ADF4153
DD
is 3 V,