TWR-ADCDAC-LTC Freescale Semiconductor, TWR-ADCDAC-LTC Datasheet - Page 70

• Manufacturer Part Number: TWR-ADCDAC-LTC
• Description: MOD ADC DAC TOWER LINEAR TECH
• Manufacturer: Freescale Semiconductor
• Type: A/Dr

Specifications of TWR-ADCDAC-LTC

• Main Purpose: Data Conversion, ADC, DAC
• Embedded: No
• Utilized Ic / Part: LTC1859, LTC2498, LTC2600, LTC2704, LTC3471
• Primary Attributes: 2 Analog to Digital Converters, 2 Digital to Analog Converters
• Secondary Attributes: For use with Freescale Tower System
• Maximum Clock Frequency: 50 MHz
• Interface Type: Touch Sense, ULPI, UART, IrDA, I2S,
• Product: Data Conversion Development Tools
• Silicon Manufacturer: Freescale
• Silicon Core Number: LTC2704, LTC2600, LTC1859, LTC2498, LTC3471 & LTC6655-5
• Kit Application Type: Data Converter
• Application Sub Type: ADC, DAC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Kinetis MCU
• Lead Free Status / Rohs Status: Compliant

►
►
►
►
►
►
Freescale Confidential and Proprietary
Freescale, the Freescale logo, CodeWarrior, ColdFire and Powerquicc are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Flexis, Processor Expert and QorIQ are
trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and
Power.org logos and related marks are trademarks and service marks licensed by Power.org. ARM is the registered trademark of ARM Limited. ARM Cortex-M4 and ARM Cortex-M3 are
trademarks of ARM Limited. © 2010 Freescale Semiconductor, Inc.
Serial Peripheral Interface bus:
Buffered transmit and receive operation with 4 entry Rx and Tx FIFOs
Programmable transfer attributes on a per-frame basis:
Up to 6 Peripheral Chip Selects, expandable with an external demultiplexer
DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
Modified SPI transfer formats for communication with slower peripheral devices
•
•
•
•
•
•
•
•
•
•
Full-duplex, three-wire synchronous transfers
Master and slave modes
Maximum master mode frequency is CPU freq/4 (ex. 100MHz/4 = 25MHz)
Maximum slave mode frequency is CPU freq/8 (ex. 100MHz/8 = 12.5MHz)
Parameterized number of transfer attribute registers (from two to six depending on device and particular
SPI instantiation)
Serial clock with programmable polarity and phase
Various programmable delays
Programmable transfer size of 4 to 16 bits
Continuously held chip select capability (for the length of the FIFO)
Exact number of chip selects depend on device and particular SPI instantiation (different SPIs on same
device can have different number of chip selects)
71
SPI Features
TM