TWR-ADCDAC-LTC Freescale Semiconductor, TWR-ADCDAC-LTC Datasheet - Page 39

• Manufacturer Part Number: TWR-ADCDAC-LTC
• Description: MOD ADC DAC TOWER LINEAR TECH
• Manufacturer: Freescale Semiconductor
• Type: A/Dr

Specifications of TWR-ADCDAC-LTC

• Main Purpose: Data Conversion, ADC, DAC
• Embedded: No
• Utilized Ic / Part: LTC1859, LTC2498, LTC2600, LTC2704, LTC3471
• Primary Attributes: 2 Analog to Digital Converters, 2 Digital to Analog Converters
• Secondary Attributes: For use with Freescale Tower System
• Maximum Clock Frequency: 50 MHz
• Interface Type: Touch Sense, ULPI, UART, IrDA, I2S,
• Product: Data Conversion Development Tools
• Silicon Manufacturer: Freescale
• Silicon Core Number: LTC2704, LTC2600, LTC1859, LTC2498, LTC3471 & LTC6655-5
• Kit Application Type: Data Converter
• Application Sub Type: ADC, DAC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Kinetis MCU
• Lead Free Status / Rohs Status: Compliant

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trademarks of ARM Limited. © 2010 Freescale Semiconductor, Inc.
• SRAM performance for core accesses:
• The on-chip SRAM is implemented with TCML:TCMU ranges forming a
contiguous block of memory. TCML is anchored to 0x1FFF_FFFF and occupies
the range before this base address. The TCMU is anchored to 0x2000_0000 and
occupies the space after this base address.
•SRAM retained in VLLS2 mode starts at TCMU 0x2000_0000
Tightly Coupled Memory Lower
Tightly Coupled Memory Upper
• Instruction fetch from TCML has zero wait states
• Instruction fetch from TCMU has one wait state
• Data fetch from TCML and TCMU have zero wait states
(TCMU) SRAM
(TCML) SRAM
0x1800_0000–0x1FFF_FFFF
0x2000_0000–0x200F_FFFF
System RAM Memory Map
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