ZL2105ALNF Intersil, ZL2105ALNF Datasheet - Page 7

• Manufacturer Part Number: ZL2105ALNF
• Description: IC DGTL DC-DC CTRLR 3A 36QFN
• Manufacturer: Intersil
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ZL2105ALNF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 200kHz ~ 2MHz
• Voltage - Input: 4.5 V ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4. Pin Descriptions (continued)
Notes:
1.
20,21
22,23
24,25
ePad
Pin
I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. Please refer to Section 4.4 “Multi-mode Pins,” on
page 12.
26
27
28
29
30
31
32
33
34
35
36
VDDL
Label
PGND
VDDP
VDDS
SGND
MGN
VRA
CFG
BST
V25
SW
VR
FC
EN
PG
7
Type
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
I/O
O
I
I
I
I
1
Description
Power ground. Common return for internal switching MOSFETs.
Switching node (level-shift common).
Bias power for internal switching MOSFETs (return is PGND).
Bootstrap V
Regulated bias from internal 5V low-dropout regulator (return is PGND). Decouple
with a 4.7 µF capacitor to PGND.
Connect 91Ω resistor between VR and VRA.
Regulated 5 V bias for internal analog circuitry (return is SGND).
Decouple with a 4.7 µF capacitor to SGND.
Connect 91Ω resistor between VR and VRA.
Internal logic supply. Connect to VRA or apply a 3.0-5.5 V external supply. Return is
SGND.
IC supply voltage (return is SGND).
Regulated bias from internal 2.5 V low-dropout regulator. Decouple with a 10µF
capacitor.
Frequency compensation select pin. Used to set loop compensation.
Signal that enables margining of output voltage.
Configuration pin. Sets switching phase delay and sequencing order.
Enable input. Active high signal enables the device.
Power good output. This pin transitions high 100 ms after output voltage stabilizes
within regulation band. Programmable open drain output. Factory default is open drain.
Exposed thermal pad. Common return for analog signals; internal connection to
SGND. Connect to low impedance ground plane.
DD
for level-shift driver (referenced to SW).
ZL2105
March 30, 2011
FN6851.2