ZL2105ALNF Intersil, ZL2105ALNF Datasheet - Page 16

• Manufacturer Part Number: ZL2105ALNF
• Description: IC DGTL DC-DC CTRLR 3A 36QFN
• Manufacturer: Intersil
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ZL2105ALNF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 200kHz ~ 2MHz
• Voltage - Input: 4.5 V ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6 Start-up Procedure
The ZL2105 follows a specific internal start-up
procedure after power is applied to the VDD pins
(VDDL, VDDP, and VDDS). Table 8 describes the
start-up sequence.
If the device is to be synchronized to an external clock
source, the clock frequency must be stable prior to
asserting
approximately 10-20 ms to check for specific values
stored in its internal memory. If the user has stored
values in memory, those values will be loaded. The
device will then check the status of all multi-mode pins
and load the values associated with the pin settings.
Once this process is completed, the device is ready to
accept commands via the I
device is ready to be enabled. Once enabled, the device
requires approximately 7 ms before its output voltage
may be allowed to start its ramp-up process. If a soft-
start delay period less than 7 ms has been configured
(using PMBus commands), the device will default to a
7 ms delay period. If a delay period greater than 7 ms
is configured, the device will wait for the configured
delay period prior to starting to ramp its output.
After the delay period has expired, the output will
begin to ramp towards its target voltage according to
the pre-configured soft-start ramp time that has been
set using the SS pin.
5.7
Table 8. ZL2105 Start-up Sequence
Step #
1
2
3
4
5
the
Internal Memory
Pre-ramp Delay
Multi-mode Pin
Power Applied
Device Ready
EN
Step Name
16
Check
Check
pin.
2
C/SMBus interface and the
The
The device loads values configured by the multi-mode
The device requires approximately 6 ms following an
The device will check for values stored in its internal
memory. This step is also performed after a Restore
device
Additional pre-ramp delay may be configured using
Input voltage is applied to the ZL2105’s VDD pins
The device is ready to accept an enable signal.
enable signal and prior to ramping its output.
requires
(VDDL, VDDP, VDDS)
ZL2105
Description
the DLY pin.
command.
pins.
In some applications, it may be necessary to set a delay
from when an enable signal is received until the output
voltage starts to ramp to its target value. In addition,
the designer may wish to precisely set the time
required for V
delay period has expired. These features may be used
as part of an overall inrush current management
strategy or to precisely control how fast a load IC is
turned on. The ZL2105 gives the system designer
several options for precisely and independently
controlling both the delay and ramp time periods.
The soft-start delay period begins when the EN pin is
asserted and ends when the delay time expires. The
soft-start delay period is set using the DLY pin.
The soft-start ramp timer enables a precisely controlled
ramp to the nominal V
delay period has expired. The ramp-up is guaranteed
monotonic and its slope may be precisely set using the
SS pin.
The soft-start delay and ramp times can be set to one of
three standard values according to Table 9 and Table
10 respectively.
Table 9. Soft Start Delay Settings
DLY Pin Setting
Soft Start Delay and Ramp Times
OPEN
HIGH
LOW
OUT
to ramp to its target value after the
OUT
Soft Start Delay Time
value that begins once the
Approx 10-20 ms (device
Depends on input supply
signal or PMBus traffic
will ignore an enable
Approximately 6 ms
during this period)
Time Duration
100 ms
10 ms
50 ms
ramp time
March 30, 2011
FN6851.2