ZL2105ALNF Intersil, ZL2105ALNF Datasheet - Page 2

• Manufacturer Part Number: ZL2105ALNF
• Description: IC DGTL DC-DC CTRLR 3A 36QFN
• Manufacturer: Intersil
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ZL2105ALNF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 200kHz ~ 2MHz
• Voltage - Input: 4.5 V ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Electrical Characteristics ............................................................................................................................................... 3
2. Pin Descriptions ............................................................................................................................................................ 6
3. Typical Application Circuit ........................................................................................................................................... 8
4. ZL2105 Overview ....................................................................................................................................................... 10
5. Power Conversion Functional Description .................................................................................................................. 13
6. Power Management Functional Description ............................................................................................................... 24
7. Package Dimensions .................................................................................................................................................... 33
8. Ordering Information .................................................................................................................................................. 34
9. Related Documentation ............................................................................................................................................... 34
10. Revision History ........................................................................................................................................................ 35
4.1 Digital-DC Architecture ........................................................................................................................................ 10
4.2 Power Conversion Overview ................................................................................................................................ 11
4.3 Power Management Overview .............................................................................................................................. 12
4.4 Multi-mode Pins .................................................................................................................................................... 12
5.1 Internal Bias Regulators and Input Supply Connections ...................................................................................... 13
5.2 High-side Driver Boost Circuit ............................................................................................................................. 13
5.3 Low-side Driver Supply Options .......................................................................................................................... 13
5.4 Dual Input Supply Configuration .......................................................................................................................... 14
5.5 Output voltage Selection ....................................................................................................................................... 15
5.6 Start-up Procedure ................................................................................................................................................. 15
5.7 Soft Start Delay and Ramp Times ......................................................................................................................... 16
5.8 Switching Frequency and PLL .............................................................................................................................. 17
5.9 Component Selection ............................................................................................................................................ 19
5.10 Current Sensing and Current Limit Threshold Selection .................................................................................... 22
5.11 Loop Compensation ............................................................................................................................................ 22
5.12 Non-linear Response (NLR) Settings .................................................................................................................. 23
5.13 Efficiency Optimized Drive Dead-time Control ................................................................................................. 24
6.1 Input Undervoltage Lockout ................................................................................................................................. 24
6.2 Power Good (PG) and Output Overvoltage Protection ......................................................................................... 25
6.3 Output Overvoltage Protection ............................................................................................................................. 25
6.4 Output Pre-Bias Protection ................................................................................................................................... 25
6.5 Output Overcurrent Protection .............................................................................................................................. 26
6.6 Thermal Overload Protection ................................................................................................................................ 26
6.7 Voltage Tracking................................................................................................................................................... 27
6.8 Voltage Margining ................................................................................................................................................ 28
6.9 I
6.10 I
6.11 Phase Spreading .................................................................................................................................................. 29
6.12 Output Sequencing .............................................................................................................................................. 30
6.13 Monitoring via I
6.14 Temperature Monitoring using the XTEMP Pin ................................................................................................. 31
6.15 Non-Volatile Memory and Device Security Features ......................................................................................... 32
2
C/SMBus Communications ................................................................................................................................ 29
2
C/SMBus Device Address Selection ................................................................................................................ 29
2
2
C/SMBus ................................................................................................................................. 31
Table of Contents
ZL2105
March 30, 2011
FN6851.2